Routing IO power pads

[pskol95]

Hello !
I have 4 pg pins in IO pad instance :
VDD, VSS - for core
VDDIO, VSSIO - for IO power

How can I route VDDIO, VSSIO ?
After verifying connectivity before gdsstream,it says-
no routing for net VDDIO, VSSIO.

Also it will be very helpful if someone can explain, how to properly procees after inserting IO pads instances in synthesized netlist before pnr till gds_streamout.

Thanks !

 

[ThisIsNotSam]

in most cases VDDIO and VSSIO are connected by abutment. you just put the IO cells side by side and they form the power structure like that.
if you really need to route, which is rare, then you use special route commands

 

[pskol95]

Okay, I have inserted IO Filler between the pads, and it shows open connectivity error all around the pads ring, also after verify_geometry it shows shorts of IO cells with IO filler(which is obvious).
What should I do ?

 

[ThisIsNotSam]

check for DRC/LVS issues in calibre. do not rely on Innovus for these checks, it will give you many false positives

 

[pskol95]

Okay thanks Sir !
For symmetry I have 2 dummy pads in the design. Can I assign the output of those dummy pad to '0' like -
wire [1:0] dum_pad;
PAD_CELL io_DUM0 ( .inout(dummy[0]), .output(dum_pad[0]) );
PAD_CELL io_DUM1 ( .inout(dummy[1]), .output(dum_pad[1]) );
assign dum_pad = 2'b0; ?

Or
What should I do ?

These pads are just for namesake, just for symmetry.

 

[ThisIsNotSam]

You can do it as you suggested, but this will likely create other problems. Innovus will interpret that dum_pad is a signal net that must be routed and will do crazy things with it. In all technologies I have experience with, filler pads have no IOs. I am not sure what is the purpose of these pins in your pad cells.

 

[pskol95]

The purpose of the PAD pin is -
one pin is "input" port
and other is "output" port.
btw is it necessary that all 4 sides of the chip i.e n s e w should have equal number of pads ?

Just to make it symmetric, I inserted these 2 dummy pads, else they are of no use in design.

Should I remove these dummy's ?
or
If I wants to maintain equal number of pads on all 4 sides, what should I do with these dummy's ?

Thanks !

 

[ThisIsNotSam]

there is no need for symmetry. in some chips we don't even have all 4 sides covered by IOs. I have made chips that had a pad ring U shaped (3 sides) and some that are L shaped (2 sides). As long as you respect ESD rules, you have some freedom to change the structure of the pad ring.

 

[pskol95]

Okay, my design is already pad limited, now I think as you said it will not be a problem to just remove these dummy's.
Thanks !

 

[pskol95]

in most cases VDDIO and VSSIO are connected by abutment. you just put the IO cells side by side and they form the power structure like that.
if you really need to route, which is rare, then you use special route commands

I have defined power & ground net as below before init_design:
set init_pwr_net { VDD VDDIO }
set init_gnd_net { VSS VSSIO } and

globalNetConnect as below after floorplanning -

globalNetConnect VDD -type pgpin -pin VDD -inst * -all -override -verbose
globalNetConnect VDD -type pgpin -pin VSS -inst * -all -override -verbose

globalNetConnect VDDIO -type pgpin -pin VDDIO -override -verbose -netlistOverride
globalNetConnect VSSIO -type pgpin -pin VSSIO -override -verbose -netlistOverride

Is it correct ?
Should I define VDDIO and VSSIO as above ?
or
It is not needed as they will be connected by abutment.

Thanks !

 

[ThisIsNotSam]

it's ok. if they are connected by abutment, there is no harm in being precise here when declaring the global nets.