regarding floorplanning

[venkatramanan]

can u anyone answer me what is the minimum space between two macros?how we can find minimum space of macros...
for best floorplan what are important points we should follow?

 

[jeevan.life]

There is no specific minimum spacing rule for macros, You can abut them as well. But depending on the number of pins and connections your macro has which talk to logic or other macros, You can space them as per the metal width and approx buffer area estimation.

For best floorplan, it is preferred to have macros around the edges of the chip and place the macros talking to each other together.
You should place appropriate blockages without fail.

 

[yadavvlsi]

The formula to calculate spacing between two macro is (width+spacing x number of pins /vertical routing layers) + spacing. It is better adding an additional spacing because you can avoid violation with the side of macros.

Tips for macro Placement

1. Place macros around chip periphery.
If you don’t have reasonable rationale to place the macro inside the core area, then place macros around the chip periphery. Placing a macro inside the core can invite serious consequence during routing due to a lot of detour routing, because macros are equal to a large obstacle for routing. Another advantage to placing the hard macros around the core periphery is it's easier to supply power to them, and reduces the change of IR drop problems to macros consuming high amounts of power.
2. Consider connections to fixed cells when placing macros.
When you decide macro position, you have to pay attention to connections to fixed elements such as I/O and perplaced macros. Place macros near their associate fixed element. Check connections by displaying flight lines in the GUI.
3. Orient macros to minimize distance between pins.
When you decide the orientation of macros, you also have to take account of pins positions and their connections.
4. Reserve enough room around macros.
For regular net routing and power grid, you have to reserve enough routing space around macros. In this case estimating routing resources with precision is very important. Use the congestion map from trialRoute to identify hot spots between macros and adjust their placement as needed.
5. Reduce open fields as much as possible.
Except for reserved routing resources, remove dead space to increase the area for random logic. Choosing different aspect ratio (if that option is available) can eliminate open fields.
6. Reserve space for power grid.
The number of power routes required can change based on power consumption. You have to estimate the power consumption and reserve enough room for the power grid. If you underestimate the space required for power routing, you can encounter routing problems.

 

[venkatramanan]

thank u so much....
another one doubt how we can do pinplacement in floorplan stage...

 

[vijayR15]

Hai venkatramanan,
Before pin placement gather the pins which are connecting with the macro block and be catious that your macro block connecting to the pins are little closer..

For pin placement

using "loadIoFile" command u can give input pin file

Ex:- loadIoFile ./pinfile.io


In that u can specify the direction pinname,offset, layer, width and depth. u can place the pin closer to the macro by changing the offset value. This value represents the exact location.


Example:

(top
(pin name="Sys_Reset_n" offset=134.13 layer=4 width=0.1000 depth=0.5200 place_status=fixed )
)


Here direction is top
width and depth represents the pin width and depth
offset value is location where u are going to place. For top pins and bottom pins values goes on increasing by left to right.
For left and right pins values goes on increasing from bottom to top.
Hope it may help you....... Thanks:razz:

 

[venkatramanan]

thank u so much..
can we change offset value in io file based on our requirement?or we have inform anyone?
or we can do manually in tool?

 

[vijayR15]

hai venkat,

ya we can change this simply using scripts by changing offset value or else we change by tool wise using move..

Onething venkat u must consult the pin placement with the top level guys becoz according to the pin placement information given by them u can order and place macros but u can give the offset value based on the needs of your requirement based on macros related to your design...

hope it may help u... thanks:razz:

 

[venkatramanan]

thank u for nice explanation...

 

[kudo1017]

What is a macro?I m a fresher for floorplanning....actually just know it in last course lab..

 

[yadavvlsi]

Macros are intellectual properties that you can directly use in use in your design. You need not to design it. For example memories, processor core, serdes, PLL etc. A macro can be hard or Soft macro.

Soft macro and Hard macro are categorized as IP's while being optimized for power, area and performance. When buying IP and evaluation study is usually made to weigh advantages and disadvantages of one type of macro over the other like hardware compatibility issues like the different I/O standards within the design, and compatibility to reuse methodology followed by design houses.

Soft macros:
Soft macros are used in SOC implementations. Soft macros are in synthesizable RTL form, are more flexible than Hard macros in terms of reconfigurability. Soft macros are not specific to any manufacturing process and have the disadvantage of being unpredictable in terms of timing, area, performance, or power. Soft macros carry greater IP protection risks because RTL source code is more portable and therefore, less easily protected than either a netlist or physical layout data. Soft macros are editable and can contain standard cells, hard macros, or other soft macros.

Hard macro:
Hard macos are targeted for specific IC manufacturing technology. They are block level designs which are optimized for power or area or timing and silicon tested. While accomplishing physical design it is possible to only access pins of hard macros unlike soft macros which allows us to manipulate the RTL. Hard macro is a block that is generated in a methodology other than place and route ( i.e. using full custom design methodology) and is imported into the physical design database (eg. Volcano in Magma) as a GDS2 file.

 

[kudo1017]

What a shame...I'm right a SOC student...and I even don't know that's the alternative name of IPs or cores, thanks for your nice answer!

 

[vijji.sami]

can u anyone answer me what is the minimum space between two macros?how we can find minimum space of macros...
for best floorplan what are important points we should follow?

There is no specific amount of space that u hav to keep in between the macros.the spaces in between the macros basically called as channels.if u have more number pins for your macro then u must n should hav to keep the space between them such that u can hav routing with no congestion n the space is also used for repeater insertion if the macros hav to communicate in a long distance.
u should keep the space between macros such that atleast one power stripe can be laid out through that channel.

i think it may help u.




[sharing is the best way of learning]

---------- Post added at 18:35 ---------- Previous post was at 18:29 ----------

can u please elaborate the terms in that formula for spacing b/n macros?

 

[praveen.kumar432]

genarally space btw macros are calcukated distance=(number of pins* pich)/(total number of available metals/2)
why we are dividing with 2 means...vertical and horijantal metals so we are dividing .

ex: i have 2 macros having the pins of 100 eatch macro and pich =0.25 and available metals are=6
then space btw 2 macros =((100+100)*0.25)/(6/3).....this much distance u should provide btw macros.

 

[prahullchintu]

distance between macro can be known from =(no. of pins of macros*pitch*2)/no. of available routing layers