pls help regarding clock divider

[gvsm]

hi there,

i need to know an example of a vhdl code for generating 1kHz and 10kHz wave as output. the frequency of the clock is 100kHz.

below is an example of code i did, bt there are errors where i cannot compile and run the code...

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;


entity clkdivider is
port (clkin : in std_logic;
C1, C2: out std_logic);

end clkdivider;

architecture beh of clkdivider is
--signal count : std_logic_vector (3 downto 0);
signal clk : std_logic := '0';
signal count : integer := '0' ;


begin
process (clkin,count)
begin
if (clkin'event and clkin = '1') then
count <= count + 1;
elsif (count =10) then
count <= '0';
end if;

if count<3 then
C1 = '1';
else
C1 = '0';
end if;

if count<7 then
C2 = '1';
else
C2 = '0';
end if;

end process;
end beh;
thank you.....[/code]

 

[j_andr]

/.../

you have some syntax errors like:
--> signal count : integer := '0'
if integer then not '0' but just the number 0;
I've changed also: C2 = '1'; to C2 <= '1';
I don't know vhdl rules enough to explain why
the first is wrong and the second ok;

at the end a logical error, look at this:

if (clkin'event and clkin = '1') then
count <= count + 1;
elsif (count =10) then
count <= '0';

elsif means if not clock slope
I'm sure it's not what you want;
you should write it similar to this:

  if (clkin'event and clkin = '1') then
    if (count =10) then count <= '0';
    else                count <= count + 1;
    end if;
  end if;

---