Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Regarding the digital gain compensation in FPGA

Status
Not open for further replies.

Maitry07

Advanced Member level 4
Joined
Jun 29, 2022
Messages
109
Helped
0
Reputation
0
Reaction score
0
Trophy points
16
Activity points
961
Hello support team,

I have a fixed gain RF chain at the input of RF-ADC(high speed data converter) , and RF-ADC has inbuilt DDC , which convert RF input direct to I, Q samples. From the I,Q samples I am using CORDIC IP core for the conversion of I, Q to amplitude and phase.
But as the original RF input amplitude is modified due to fixed gain RF chain, I want to compensate for that fixed RF gain , so that I can get the exact amplitude after CORDIC.
So, for that in between DDC output(I, Q samples) and CORDIC input , I need to add digital gain compensation algorithm.
Could anyone suggest a suitable way to do this digital gain compensation?
My RF input is sine wave ( no modulation)- 65 MHz frequency.
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top