Need help regarding HDL terminology

[Tajira]

I am trying to simulate a sensor input into my VHDL design. Now I need a component within the testbench that mimics that sensor. I am thinking about asking the manufacturer of the sensor to provide some sort of simulation model for that sensor so that I may use it in my VHDL testbench.
What is the exact term used for such simulation models, that I should use while asking the manufacturer for such a component?

 

[FvM]

They are called "simulation model", provided as VHDL or more often Verilog behavioral description. But I think it's rather unlikely that you get a simulation model for a digital sensor. Vendor models are e.g. available for DDR memory.

If you need the model to verify the operation of your design, you are most likely required to write it yourself.