Phase Shifted Full Bridge converter intial testing procedure

[sabu31]

Hi all,

I am testing a PSFB conversation. I have used the application note of TI and also the IC UCCC28950. I am giving 12 V separately and the DC voltage input is given through a rectifier with a variac.

Initially the bias 12V is kept on. Then I am ramping up the input voltage from zero. Initially, the system is operational (ie the pulses are generated ), when the input voltage crosses 60V, it goes into a burst mode/reset mode.
The required Output is 12V, The input voltage ideal is 400V. The load resistance is kept at 5 ohms for initial troubleshooting.

What could be the reason for this burst mode operation.

 

[FvM]

Not much info. What is resetting? Burst mode is a feature of UCCC28950, started when pulse width becomes too low.

 

[D.A.(Tony)Stewart]

" it waits until the converter is demanding a duty cycle equal or higher than TMIN before the controller puts out TMIN or a PWM duty cycle as dictated by COMP voltage pin."

The higher the Vin, the lower df of PWM will be, then Tmin can be reduced with Rtmin =10k

 

[sabu31]

Dear All,

Sorry for the late reply.

I am attaching waveforms of the IC28950 pins such as CS,SS,COMP, EA- and also transformer primary. I am also attaching the schematic used.


The final requirement is 1.5kW at 48V. However for initial testing, I have changed the sense resitor to get a voltage of 24 V in output(Input is varied from 0 to 150V). I am attaching waveforms captured in attached pdf. The load resistance presently used is 4 Ohms. The transformer primary inductance is 2.6mH and leakage inductance is 7uH. I am not using any shim inductance.


The key observation is that the transformer voltage is nearly square wave. Once system reaches 24V, any further increase in input voltage the system goes to burst mode.

Also it is observed that the Gate Voltage of QA starts dipping and then nearly turns of as the system output voltage reaches 24V. I am also attaching updated daughter board schematic values.

How should I troubleshoot the issue.

 

[D.A.(Tony)Stewart]

List assumptions, show layout, compare differences with Demo board. https://www.ti.com/seclit/df/tidrbx3/tidrbx3.pdf