Netlist Problem Regarding nets specification

[priyanka22]

Hello All

I am facing regularly netlist regarded problems as I am on the way to generate netlist for my VHDL code.
For me Netlist means to know the exact structure of Gates or nets used in the VHDL code implementation.
I have generated .ngc file & .ngd file through synthesis and schematic generation now what should be the next step in the way generating netlist.
I am using ISE Project Navigator 12.4
Kindly help me through your valuable experiences.
Thank you all for going through my post!

~With Regards
Priyanka Singh

 

[milind.a.kulkarni]

In my view Priyanka you are working on Xilnix FPGA ..... In order to view the extact structure of GATEs and nets u need to go the ISE Synthsis option and view RTL schematic .....
That will give you the module wise overview of the VHDL and View Technology schematic will give u GATE and net level diagram.....However I had not used VHDL so extensively ....As I am an user of Verilog....

I think that should help

Good Luck

 

[priyanka22]

Thank you sir for helping but I had gone all the steps you have mentioned above. I just don't want the schematic diagrams of internal nets only, I also need the whole written specification of how much logic is involved at lower level.

Thank you!

~With Regards
Priyanka Singh

 

[milind.a.kulkarni]

Here is schematic that I got for one of my code......



---------- Post added at 16:14 ---------- Previous post was at 16:12 ----------

ok for that you need to open the synthesis report ...... that will give you the description that you are intended....it is at the same location of synthesis tab....

Good Luck

 

[priyanka22]

Ok sir I will check that.
But that will not be sufficient as I required such description which has some format of nets. Don't know the file extension yet.
Anyways Thanx for concern!

~With Regards
Priyanka Singh

 

[milind.a.kulkarni]

I think you refer this-

**broken link removed**

good luck