MBIST controller for Syncronous and asynchronous DRAM

[Gireesh]

hi,

I want to design a MBIST controller for both sync and async DRAM cells. The algorithm that i decided to implement is March C-- algorithm.

Please someone help me

 

[rameshsuthapalli]

Hi,

i dont understand you requrement. do u want to design the Mbist compiler or u want to design the controller which will test the given memory.

regards,
ramesh.s

 

[Gireesh]

Hi ramesh,

i want to design a Mbist controller which can be used for testing of both the memories.

 

[yln2k2]

Hi ,

Actually tools from mentro do the same . If your company have license you can invoke the tool and u can generate mbist controller design for the same .

If you want to design your self
1) You need to design interface of bist controller compatable with memory
2) Implement algorithum in RTL
3) If you want to do the same in SOC some how you should intiate bist and mechanisum from pass/fail etc ...

could you pelase elobarate exact req ... based on that i will try to elobarate ...


Thanks & Regard
yln

 

[rameshsuthapalli]

Hi,
i am useing the mentor tools but inorder to debug the problems i need the some documentations of the basic one so please help me in that

 

[SMason]

I used to write some code on VHDL. If you need, i can send it to you.