abaz
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Taking into account my clearance constraints and polygon pours for power supply nets on a BGA device, I find that I'm not getting much connection metal between the vias that are not power supply ones.
If I have full stack vias going through a multi layer board and decide to remove via pads on layers that the via is just passing through is this a problem for PCB manufacturers or can they all do it. I'm particularly interested if this is possible on the top and bottom layers, where I can make the pad diameter the same as the hole size, giving me more width in my polygon pours or traces going inbetween vias
Any thoughts or experience on this matter would be greatly appreciated
If I have full stack vias going through a multi layer board and decide to remove via pads on layers that the via is just passing through is this a problem for PCB manufacturers or can they all do it. I'm particularly interested if this is possible on the top and bottom layers, where I can make the pad diameter the same as the hole size, giving me more width in my polygon pours or traces going inbetween vias
Any thoughts or experience on this matter would be greatly appreciated