OvErFlO
Full Member level 3
How can I manage a asynchonous signal without metastability problem ?
I receive a asynchonous signal in my FPGA and I must read streaming bits data... How can I synchonized my internal clock with external stream ?
I have read that I can resolve this problem with a FlipFlip D... but there is a Metastability problem when clock and stream have the same edge...
How can I resolve this ?
thanks...
I receive a asynchonous signal in my FPGA and I must read streaming bits data... How can I synchonized my internal clock with external stream ?
I have read that I can resolve this problem with a FlipFlip D... but there is a Metastability problem when clock and stream have the same edge...
How can I resolve this ?
thanks...