Management of a Asynchronous signal

[OvErFlO]

How can I manage a asynchonous signal without metastability problem ?
I receive a asynchonous signal in my FPGA and I must read streaming bits data... How can I synchonized my internal clock with external stream ?

I have read that I can resolve this problem with a FlipFlip D... but there is a Metastability problem when clock and stream have the same edge...
How can I resolve this ?

thanks...

 

[shiva_mag]

if you use two D ff's in series then problem can be solved.If the edge of stream and clock are same first ff may go into metastable state but, before the second ff latches this this first ff would have come out of metastable state.Metastable state won't last for long duartion.

 

[brmadhukar]

Hi,
What about the rates of incoming and processing? If incoming is slower you can just use a buffer.
BRMadhukar

 

[hyperion007]

you may read <Synthesis and Scripting Techniques for Designing Multi-
Asynchronous Clock Designs>

 

[OvErFlO]

Where can I find this article ?

Thanks

 

[shiva_mag]

read this article on asynchronous clock design by clifford cummings

 

[Black Jack]

***
... but there is a Metastability problem when clock and stream have the same edge...
How can I resolve this ?

thanks...

For data stream e.g. 10 Mbit/s you need 20 MHz
Use PLL from Data stream for Synchronization
and choose right edge (rise or fall)
____/''''''''''\_____/''''''''''\___ -DATA
__/''''\__/''''\__/''''\__/''''\____ Clock (rise)