INOUT example (XC95144XL)

[TheBorg]

Hi.

I have for some days ago written a subject about using INOUT in a VHDL design, i all got a responce on putting the INOUT bus in 'Z' state before reading, but that i allready had done.

I use the 'Generate Expected Simulation Results' the only two state a can put on is for now '1' and '0', but not read from the bus ?

Any help on the issue is very welcome, a just dont now what to do any more. Source below:


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;


entity Counter is
Port ( EXT_SYS_Clock : in std_logic;
EXT_SRAM_Data : inout std_logic_vector(7 downto 0);
EXT_LATCH_Data : out std_logic_vector(7 downto 0));
end Counter;


architecture Behavioral of Counter is
TEST: process (EXT_SYS_Clock)
begin
if (EXT_SYS_Clock' event and EXT_SYS_Clock = '1') then
EXT_SRAM_Data <= "ZZZZZZZZ";
EXT_LATCH_Data <= EXT_SRAM_Data;
end if;

end process;

end Behavioral;


Thanks for your help in advance.

Best regards

René

 

[echo47]

You can't clock Z's into a register. Pretend you are hooking up TTL chips. You connect an 8-bit register to an 8-bit three-state driver. The register stores 1's and 0's only, and has a clock input. The three-state driver has an enable input, and operates like a combinatorial multiplexer - when enable is high it outputs the 8-bit input data, when enable is low it outputs all Z's. That will work in HDL too.

 

[TheBorg]

Thanks alot for you help, but i am afraid that i dont understand how to combine this knowlegde with the INOUT term, do you may or could you give a short example in VHDL on how to read write from a databus ?

Im sorry asking for this kind of help but simply complete stucked on the issue.

Thanks a lot for help in advance.


Best regards

René

 

[tkbits]

Here is the way I've used VHDL Z-state in the past, where DATABUS is an INOUT port.

-- Select a register to read using appropriate read-enable signal
-- NOTE:  The output buffers of the external data supplier must also be
--   driven into the Z state.
-- The synthesis tool will generate 3-state buffers.
DATABUS <= REG1_OUT when REG1_READ_EN = '1' else "ZZZZZZZZ";
DATABUS <= REG2_OUT when REG2_READ_EN = '1' else "ZZZZZZZZ";

-- You can use DATABUS directly as input.
-- The following will set DATABUS_ZERO to "true" whenever DATABUS is 0,
--   regardless of where the zero came from (e.g., it can come from REG1_OUT).

DATABUS_ZERO <= '1' when DATABUS = X"00" else '0';

-- Update registers using appropriate write-enable signal.
-- Use registers to "capture" input data.

U_REG1: process (clk)
begin
   if rising_edge(clk) then
      if REG1_WRITE_EN = '1' then
         REG1_OUT <= DATABUS;
      end if;
   end if;
end process;

U_REG2: process (clk)
begin
   if rising_edge(clk) then
      if REG2_WRITE_EN = '1' then
         REG2_OUT <= DATABUS;
      end if;
   end if;
end process;

 

[echo47]

Here's an example:
http://www.altera.com/support/examples/vhdl/v_bidir.html