Getting a warning from my VHDL simulation using inout

[FPGAwarrior]

I am building from existing core VHDL code. It is using two GPIOS for all the INs and OUTs. Initially one bank was IN and the other OUT. As my project made me create more complex PCBs, I had to define the GPIOs as inout.
Here is a reduced form of my code:

entity s_k_top is
port(
          gpio_1_inout       : inout   std_logic_vector(35 downto 0);  --
          gpio_0_inout       : inout   std_logic_vector(35 downto 0);
);
    signal gate                      : unsigned(5 downto 0):= to_unsigned(0, 6); -- used as a reference to trigger processes.
begin
-- several processes and pages of code...
-- One process is the gate keeper which uses a value named "gate" to call some processes sequentially.
-- Definition of primitives
        gpio_1_inout(0) <= tst_led(13)  when gate >= 3  else 'Z';--                        pin1 -- I want all of my GPIOs to start as input upon power-on.
        gpio_1_inout(1) <= tst_led(14)  when gate >= 3  else 'Z';--                        pin2

        gpio_0_inout(34) <= B3          when gate >= 3  else 'Z';--                          pin39 B3
        gpio_0_inout(35) <= pf_shutter  when gate >= 3  else 'Z';--                      pin40 B2

Now for my testbench code:

entity tb_s_k_top is
end tb_s_k_top;

architecture tb of tb_s_k_top is
    signal gpio_0_inout         : std_logic_vector (35 downto 0);
     signal gpio_1_inout         : std_logic_vector (35 downto 0);

begin
    uut : entity work.s_k_top

    port map (CLK               => CLK,
             gpio_0_inout      => gpio_0_inout,
              gpio_1_inout      => gpio_1_inout,
);

end tb

When I run the simulation in ModelSim, I get the following:

# ** Warning: (vsim-8684) No drivers exist on inout port /tb_s_k_top/uut/gpio_1_inout(35), and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /tb_s_k_top/gpio_1_inout(35).
# ** Warning: (vsim-8684) No drivers exist on inout port /tb_s_k_top/uut/gpio_1_inout(34), and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /tb_s_k_top/gpio_1_inout(34).

How do I avoid these warnings?

 

[Akanimo]

There are no assignments in your testbench. Are these all the warnings? What about the other gpios?

Is the gatekeeper process supposed to be part of the synthesizable structure or just for simulation?

 

[FPGAwarrior]

All GPIOs are used. Similar ones give similar results.

By assignments, do you mean...
signal gpio_0_inout : std_logic_vector (35 downto 0):= (others <= 'Z') ;
signal gpio_1_inout : std_logic_vector (35 downto 0):= (others <= 'Z') ;

I added that change and got the same results.

 

[Akanimo]

All GPIOs are used. Similar ones give similar results.

By assignments, do you mean...
signal gpio_0_inout : std_logic_vector (35 downto 0):= (others <= 'Z') ;
signal gpio_1_inout : std_logic_vector (35 downto 0):= (others <= 'Z') ;

I added that change and got the same results.

No, I meant passing stimulus in your test bench. Have you done that? If yes, then let's see your updated test bench code.

 

[Akanimo]

Also, please clarify:

Is changing the mode of the ports from in and out to input all you did? Didn't you also modify the body of the code to suit the change?

 

[FPGAwarrior]

I found in some VHDL text that I had my start-up groups out of order. I now have a question about a stimulus in my TB. I will start a new post.