Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
You should refer to the transistor level schematics of NOR and AND gate in your text book.
It's no exactly clear, if the problem refers to gate input capacitances or total node capacitances (including output transistors). I assume the former, otherwise different capacitance values (Cgd, Cgd, Cds) needs to be considered.
P.S.: You really should have a look at the transistor level circuits. This is obviously the purpose of thehomework problem. As a shortcut, you can consider that basic CMOS gates have two transistors (one N and one P) connected to each input. Now count transistors.
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
