Help in Digital Converter with VHDL

[echo47]

Here's a simple DDS module (in Verilog) that I wrote long ago. It uses the full width of the Xilinx Block RAM, so you get 18-bit sine and cosine outputs. I directly instantiated and initialized the Block RAM simply because I didn't want to clutter my project with a separate initialization file, or with a "case" statement 1024 lines long. If you are wondering how I generated those initialization values, I used MATLAB.

This DDS module runs about 320 MHz in a Virtex-4. I have a fancier version with a pipelined accumulator that reaches 500 MHz. The Xilinx DDS v5.0 core runs about 340 MHz. You should check the performance of your overall design before handing it off to the next student. You don't want to give him a design that's impossible to implement.

By the way, I don't think you can realistically reach 500 MHz, because that's the maximum frequency of a Virtex-4 Block RAM before considering clock jitter.

I'll look into your filter question maybe a little later today.

module dds (clk, freq, cos, sin);
  parameter                 pbits = 32;     // phase accumulator bits
  input                     clk;
  input         [pbits-1:0] freq;           // (1 << pbits) * fout / fclk
  reg           [pbits-1:0] phase = 0;
  reg                 [9:0] addrcos = 10'h100, addrsin = 0;
  output signed      [17:0] cos, sin;       // quadrature sinewave

  always @ (posedge clk) begin
    phase <= phase + freq;
    addrcos <= phase[pbits-1:pbits-10] + 10'h100;
    addrsin <= phase[pbits-1:pbits-10];
  end

  // Tabulated sinewave ROM, 1024 points, 18 bits
  RAMB16_S18_S18 ROMsin (.CLKA(clk), .CLKB(clk), .DIA(16'd0), .DIPA(2'd0), .ADDRA(addrcos),
      .ENA(1'b1), .WEA(1'b0), .DOA(cos[17:2]), .DOPA(cos[1:0]), .DIB(16'd0), .DIPB(2'd0),
      .ADDRB(addrsin), .ENB(1'b1), .WEB(1'b0), .DOB(sin[17:2]), .DOPB(sin[1:0]));
  defparam ROMsin.INIT_00 =256'h0BC30AFB0A33096A08A207D907100647057F04B603ED0324025B019200C90000;
  defparam ROMsin.INIT_01 =256'h1833176D16A815E2151B1455138E12C81201113A10720FAB0EE30E1B0D530C8B;
  defparam ROMsin.INIT_02 =256'h246723A622E522232161209F1FDC1F1A1E561D931CCF1C0B1B471A8219BD18F8;
  defparam ROMsin.INIT_03 =256'h30412F872ECC2E112D552C992BDC2B1F2A6129A328E52826276726A825E82528;
  defparam ROMsin.INIT_04 =256'h3BA53AF23A40398C38D93824376F36BA3604354D349633DE3326326E31B530FB;
  defparam ROMsin.INIT_05 =256'h467545CD4524447A43D04325427A41CE412140733FC53F173E683DB83D073C56;
  defparam ROMsin.INIT_06 =256'h50974FFB4F5E4EBF4E204D814CE04C3F4B9D4AFB4A5849B4490F486947C3471C;
  defparam ROMsin.INIT_07 =256'h59F3596458D4584257B0571D568A55F5556054C95432539B5302526951CE5133;
  defparam ROMsin.INIT_08 =256'h627161F0616F60EC60685FE35F5D5ED75E4F5DC75D3E5CB45C285B9D5B105A82;
  defparam ROMsin.INIT_09 =256'h69FD698C691968A6683267BC674666CF665765DD656364E8646C63EF637162F1;
  defparam ROMsin.INIT_0A =256'h708370226FC16F5E6EFB6E966E306DC96D626CF96C8F6C246BB76B4A6ADC6A6D;
  defparam ROMsin.INIT_0B =256'h75F475A57555750474B2745F740B73B5735F730772AE725571FA719E714070E2;
  defparam ROMsin.INIT_0C =256'h7A417A0579C8798A794A790978C77884784077FA77B3776C772376D9768D7641;
  defparam ROMsin.INIT_0D =256'h7D627D397D0F7CE37CB77C897C5A7C297BF87BC57B917B5C7B267AEF7AB67A7C;
  defparam ROMsin.INIT_0E =256'h7F4D7F387F217F097EF07ED57EBA7E9D7E7F7E5F7E3F7E1D7DFA7DD67DB07D8A;
  defparam ROMsin.INIT_0F =256'h7FFF7FFD7FFA7FF67FF07FE97FE17FD87FCD7FC27FB57FA77F977F877F757F62;
  defparam ROMsin.INIT_10 =256'h7F757F877F977FA77FB57FC27FCD7FD87FE17FE97FF07FF67FFA7FFD7FFF7FFF;
  defparam ROMsin.INIT_11 =256'h7DB07DD67DFA7E1D7E3F7E5F7E7F7E9D7EBA7ED57EF07F097F217F387F4D7F62;
  defparam ROMsin.INIT_12 =256'h7AB67AEF7B267B5C7B917BC57BF87C297C5A7C897CB77CE37D0F7D397D627D8A;
  defparam ROMsin.INIT_13 =256'h768D76D97723776C77B377FA7840788478C77909794A798A79C87A057A417A7C;
  defparam ROMsin.INIT_14 =256'h7140719E71FA725572AE7307735F73B5740B745F74B27504755575A575F47641;
  defparam ROMsin.INIT_15 =256'h6ADC6B4A6BB76C246C8F6CF96D626DC96E306E966EFB6F5E6FC17022708370E2;
  defparam ROMsin.INIT_16 =256'h637163EF646C64E8656365DD665766CF674667BC683268A66919698C69FD6A6D;
  defparam ROMsin.INIT_17 =256'h5B105B9D5C285CB45D3E5DC75E4F5ED75F5D5FE3606860EC616F61F0627162F1;
  defparam ROMsin.INIT_18 =256'h51CE52695302539B543254C9556055F5568A571D57B0584258D4596459F35A82;
  defparam ROMsin.INIT_19 =256'h47C34869490F49B44A584AFB4B9D4C3F4CE04D814E204EBF4F5E4FFB50975133;
  defparam ROMsin.INIT_1A =256'h3D073DB83E683F173FC54073412141CE427A432543D0447A452445CD4675471C;
  defparam ROMsin.INIT_1B =256'h31B5326E332633DE3496354D360436BA376F382438D9398C3A403AF23BA53C56;
  defparam ROMsin.INIT_1C =256'h25E826A82767282628E529A32A612B1F2BDC2C992D552E112ECC2F87304130FB;
  defparam ROMsin.INIT_1D =256'h19BD1A821B471C0B1CCF1D931E561F1A1FDC209F2161222322E523A624672528;
  defparam ROMsin.INIT_1E =256'h0D530E1B0EE30FAB1072113A120112C8138E1455151B15E216A8176D183318F8;
  defparam ROMsin.INIT_1F =256'h00C90192025B032403ED04B6057F0647071007D908A2096A0A330AFB0BC30C8B;
  defparam ROMsin.INIT_20 =256'hF43CF504F5CDF695F75EF826F8EFF9B8FA81FB4AFC12FCDBFDA4FE6EFF370000;
  defparam ROMsin.INIT_21 =256'hE7CCE892E958EA1EEAE4EBAAEC71ED38EDFFEEC6EF8DF055F11CF1E4F2ACF374;
  defparam ROMsin.INIT_22 =256'hDB98DC59DD1ADDDCDE9EDF60E023E0E6E1A9E26CE330E3F4E4B8E57DE642E707;
  defparam ROMsin.INIT_23 =256'hCFBED078D133D1EFD2AAD367D423D4E1D59ED65CD71AD7D9D898D958DA17DAD8;
  defparam ROMsin.INIT_24 =256'hC45BC50DC5C0C673C727C7DBC890C946C9FCCAB2CB69CC21CCD9CD91CE4ACF04;
  defparam ROMsin.INIT_25 =256'hB98ABA33BADBBB85BC2FBCDABD85BE32BEDEBF8CC03AC0E8C198C248C2F8C3A9;
  defparam ROMsin.INIT_26 =256'hAF68B004B0A2B140B1DFB27EB31FB3C0B462B504B5A8B64CB6F0B796B83CB8E3;
  defparam ROMsin.INIT_27 =256'hA60CA69BA72CA7BDA84FA8E2A976AA0AAAA0AB36ABCDAC65ACFDAD97AE31AECC;
  defparam ROMsin.INIT_28 =256'h9D8E9E0F9E919F149F97A01CA0A2A128A1B0A238A2C1A34CA3D7A463A4F0A57D;
  defparam ROMsin.INIT_29 =256'h9602967496E6975997CD984398B9993099A99A229A9C9B179B939C119C8F9D0E;
  defparam ROMsin.INIT_2A =256'h8F7C8FDD903E90A19104916991CF9236929E9307937193DC944894B595239592;
  defparam ROMsin.INIT_2B =256'h8A0C8A5A8AAA8AFB8B4D8BA08BF58C4A8CA08CF88D518DAB8E068E628EBF8F1D;
  defparam ROMsin.INIT_2C =256'h85BE85FA8637867686B586F68738877B87C08805884C889488DC8927897289BE;
  defparam ROMsin.INIT_2D =256'h829D82C682F1831C8349837783A683D68407843A846E84A384D9851085498583;
  defparam ROMsin.INIT_2E =256'h80B280C880DE80F68110812A81468163818181A081C181E282058229824F8275;
  defparam ROMsin.INIT_2F =256'h800080028005800A800F8016801E80278032803E804A805980688079808B809E;
  defparam ROMsin.INIT_30 =256'h808B807980688059804A803E80328027801E8016800F800A8005800280008000;
  defparam ROMsin.INIT_31 =256'h824F8229820581E281C181A0818181638146812A811080F680DE80C880B2809E;
  defparam ROMsin.INIT_32 =256'h8549851084D984A3846E843A840783D683A683778349831C82F182C6829D8275;
  defparam ROMsin.INIT_33 =256'h8972892788DC8894884C880587C0877B873886F686B58676863785FA85BE8583;
  defparam ROMsin.INIT_34 =256'h8EBF8E628E068DAB8D518CF88CA08C4A8BF58BA08B4D8AFB8AAA8A5A8A0C89BE;
  defparam ROMsin.INIT_35 =256'h952394B5944893DC93719307929E923691CF9169910490A1903E8FDD8F7C8F1D;
  defparam ROMsin.INIT_36 =256'h9C8F9C119B939B179A9C9A2299A9993098B9984397CD975996E6967496029592;
  defparam ROMsin.INIT_37 =256'hA4F0A463A3D7A34CA2C1A238A1B0A128A0A2A01C9F979F149E919E0F9D8E9D0E;
  defparam ROMsin.INIT_38 =256'hAE31AD97ACFDAC65ABCDAB36AAA0AA0AA976A8E2A84FA7BDA72CA69BA60CA57D;
  defparam ROMsin.INIT_39 =256'hB83CB796B6F0B64CB5A8B504B462B3C0B31FB27EB1DFB140B0A2B004AF68AECC;
  defparam ROMsin.INIT_3A =256'hC2F8C248C198C0E8C03ABF8CBEDEBE32BD85BCDABC2FBB85BADBBA33B98AB8E3;
  defparam ROMsin.INIT_3B =256'hCE4ACD91CCD9CC21CB69CAB2C9FCC946C890C7DBC727C673C5C0C50DC45BC3A9;
  defparam ROMsin.INIT_3C =256'hDA17D958D898D7D9D71AD65CD59ED4E1D423D367D2AAD1EFD133D078CFBECF04;
  defparam ROMsin.INIT_3D =256'hE642E57DE4B8E3F4E330E26CE1A9E0E6E023DF60DE9EDDDCDD1ADC59DB98DAD8;
  defparam ROMsin.INIT_3E =256'hF2ACF1E4F11CF055EF8DEEC6EDFFED38EC71EBAAEAE4EA1EE958E892E7CCE707;
  defparam ROMsin.INIT_3F =256'hFF37FE6EFDA4FCDBFC12FB4AFA81F9B8F8EFF826F75EF695F5CDF504F43CF374;
  defparam ROMsin.INITP_00=256'hD3F23C4FD3DFD07B47A47D0E33282BD7D444B784A6DCDA6F70EC08BFE21B0540;
  defparam ROMsin.INITP_01=256'h5469C480C530315D52037F9BF8692C4E1AA36C0E776F00FA4E793943F06DE4C1;
  defparam ROMsin.INITP_02=256'h0C6DE43F05B1B6C6BC03E776C0E72A92C4E1A4BF9BF70215D530314C084DA457;
  defparam ROMsin.INITP_03=256'h0543922FF880EC37E69CDE684B78445F5FA0A332C1F46B47B41FDF1FC4F23F1D;
  defparam ROMsin.INITP_04=256'h715214C5717570D9CDACD7061128297D7CCC9D8CAE747AE5D064089562390FC0;
  defparam ROMsin.INITP_05=256'hFCEB4C804F1013F7F201D5B958EB24C63AA1E406DDE5005AC6DB1BC150E76C43;
  defparam ROMsin.INITP_06=256'h04E76C150F939E4E94016DDE406D2AB24C63AC95B95D023F7F1013C408C7ACFD;
  defparam ROMsin.INITP_07=256'h0FC1B2255880641D6EB476E8C9D8CCF5F5A0A112435CE9CD9C3575354C521537;
endmodule

 

[YenYu]

Wow... nice work for the verilog. I know the veri basics of MatLab onli. I would like to learn how to generate from MatLab but i dont haf the program.
I'll inform my teacher to see if changing to a Virtex-5 is possible with this project. And how do u know that Xilinx DDS v5.0 Core runs at 340MHz?

By the way, wat u mean by clock jitter?

Oh, Thanks for helping mi for looking into my Filter question ^_^!

 

[echo47]

I can't share my MATLAB code because I created it for a client, sorry. The code isn't very interesting though. It starts out like my little C program (above), then adds some confusing hex string manipulations.

I tried synthesizing the DDS v5.0 core all by itself in the fastest grade Virtex-4. I used all the speed optimizations that I could think of. The best speed I saw was around 340 MHz.

The DDS v5.0 core is not available for Virtex-5. You would need to use the newer DDS Compiler core. I haven't tried it.

All clocks suffer from some amount of phase jitter. The clock period varies randomly from cycle to cycle. The Xilinx DCM block is a significant source of jitter. For example, the average period of your 500 MHz clock is 2.0 ns, but the individual cycles vary from maybe 1.9ns to 2.1ns (that's just a wild guess, the real values are buried in data sheets). If your clock's minimum period is 1.9ns, then you must design your FPGA logic to run at 526 MHz, not 500 MHz. (That's too fast for a Virtex-4 Block RAM.)

More jitter info:
**broken link removed**

I had trouble viewing the filter graph. First, Project Navigator was trying to read files from your private "Documents and Settings" folder, which doesn't exist on my system. Next, it wouldn't accept the Coefficient_Width parameter in your COE files, so I deleted them. This was probably complicated by ISE having to convert the project from version 8.1i to 9.1i. This is a good example of why I normally never use cores or Project Navigator! Anyway, I now see the filter graph. Assuming your filter clock rate is 250 MHz, then the graph's X-axis goes from 0 to 125 MHz. Looks like the filter begins rolling off above about 60 MHz.

At X = 1.0,
(1.0*pi radians/sample) * (250M samples/second) / (2*pi radians/cycle) = 125M cycles/second = 125 MHz

 

[YenYu]

Hmm... Alrite i've the same problems as u at my home. It looks like using the core giving quite lots of problems... but i manage to recrea8 the filter and loading the COE file at home... so it should be alrite.

For the filter magnitude response graph, seeing from ur view, it looks like it's ard 60MHz, but reading from wikipedia, it says the cut-off frequency of a graph is maximum - 3dB from the magnitude axis. I'm kinda confuse with this, but seeing ur theory, i'm quite able to understand but still need alil help.

Next, sry for so much question... Let's say, now cut-off frequency, how to look at the amplitude of my produced wave? Cos i've to check on whether my filter is really working the correct way. This should be ard my last few task...

Thx alot bro! xD. Also thx for the jitter explanation and web =P!
Btw, how to get a new version of the DDS complier core? If i manage to get it, will it give the same problems like the spikes? Since i've look at the different of Virtex4 and Virtex 5. Virtex 5 is way too powerful then 4 just 1 or 2 lowering difference but doesnt affect my project.

 

[echo47]

Below (graph1.gif) is what I see when I load coef_32tap.coe into the FIR core. Does it match your graph?

Instead of trying to read the tiny coregen graph, it would be better to obtain filter frequency response data from whoever designed it. Or you could feed the COE file coefficients into MATLAB, and calculate the frequency response data. (MATLAB is a wonderful engineering tool.) Below (graph2.gif) is a MATLAB plot with a linear amplitude scale, which should be easier to compare to ModelSim's display.

Here's my MATLAB code:

% Given the FIR filter taps, calculate and plot the frequency response.
coeff = hex2dec(['001'; 'ff7'; 'ffe'; '014'; 'fff'; 'fd7'; '009'; '04b'; ...
                 'fe3'; 'f81'; '04a'; '0d5'; 'f50'; 'e6f'; '21c'; '76b'; ...
                 '76b'; '21c'; 'e6f'; 'f50'; '0d5'; '04a'; 'f81'; 'fe3'; ...
                 '04b'; '009'; 'fd7'; 'fff'; '014'; 'ffe'; 'ff7'; '001']);
coeff = coeff - 4096 * (coeff >= 2048);
[h w] = freqz(coeff);       % frequency response of filter
f = 250 * w / (2 * pi);     % frequency values
a = abs(h);                 % gain values
plot(f, a); grid on; xlim([0 125]); ylim([0 4500]); xlabel('Frequency [MHz]'); ylabel('Gain');
set(gca,'XTick',0:10:125,'YTick',0:500:5000,'XMinorGrid','on','YMinorGrid','on');

The term "cut-off" sometimes means different things to different people. The -3dB point (around 62 MHz) is one common interpretation. However, some people say cut-off occurs at the stop band (around 78 MHz).

Try feeding different frequencies into your HDL filter, and record the amplitudes you see. You can use ModelSim's cursor to measure the sinewave peak value. If you plot those measurements, they should match the filter graphs.

To get the new DDS Compiler core, you probably need to upgrade ISE, install the various service packs and IP updates, rebuild your simulation libraries, and then fix whatever unexpected upgrade problems you encounter. That can be a big chore.

The DDS Compiler v2.0 seems to avoid the evil -512 value that causes your overflow spikes.

 

[YenYu]

Oh yeah.... the (graph1.gif) matchs wat i see from coregen. From wikipedia's theory of cut-off frequency, it's ard 72.5db to 73db which is the maximum magnitude, and the cut-off region i interpretate is rought 69.5-70dB.

However, some people say cut-off occurs at the stop band (around 78 MHz).

I was wondering why, cos the maximum magnitude doesnt hit 80dB. Or should it be ard 68dB?

Try feeding different frequencies into your HDL filter, and record the amplitudes you see. You can use ModelSim's cursor to measure the sinewave peak value. If you plot those measurements, they should match the filter graphs.

Thkx for the help on this. xD!

Hmm, on the new core for the DDS compiler, i guess i'll try on my home desktop. It's loaded with 9.1i ISE webpack, so it should be easier. In sch, many installation & updating is restricted, preventing student from abusing.

The DDS Compiler v2.0 seems to avoid the evil -512 value that causes your overflow spikes.

Guess there's no way to solve unless to get the new Core compiler, or creat8ing ur own DDS like wat u've said b4.

I'll update you on my results on the filter on a table format that my supervisor asked mi to do. It's on tallying the cut-off region and the amplitude of the output (It2,Qt2) of different frequency.

Added after 12 minutes:

Oh ya, i've got a question i forget to ask.

At X = 1.0,
(1.0*pi radians/sample) * (250M samples/second) / (2*pi radians/cycle) = 125M cycles/second = 125 MHz

How do u manage to get the outcome 125MHz. I cant get the ans, i guess there is some conversion in between?

Added after 1 hours 35 minutes:

Hm.. Here's a lil problem. I got the binary and decimal format of my amplitude of my waveform, but then how do i convert it into MHz or dB to tally with the filter magnitude response graph?

 

[echo47]

I updated my graph2.gif and MATLAB code to show actual filter gain, instead of normalizing it to 1.0.

What is "ard"?

When I said "78 MHz", I think maybe you read "78 dB".

The graph's 80dB line is irrelevant. It is merely the top of a piece of graph paper. Maybe you are confusing it with "-3dB from the magnitude axis", which does not apply to the Xilinx graph.

My equation works out to 125 MHz. Try again.

You can estimate the frequency of the sinewave you see in ModelSim by counting the number of sinewave cycles between two points in time, and then divide the number of cycles by the elapsed time. It may help to use two cursors.

To calculate the filter's gain in dB, measure the filter's input amplitude and output amplitude, and then calculate:
dB = 20 * log10(output_amplitude / input_amplitude)

There are better ways to measure frequency and amplitude, but these methods are easy and should give approximately correct results.

 

[YenYu]

Sry, Ard means around.

kay, i get wat u mean. Hmm.. from the xilinx graph, is there any way of converting the normalised frequency to the normal frequency?

Added after 25 minutes:

Just got some info from my supervisor.
Basically, he wants to know from that Coregen Graph, wat is the cut-off frequency, and how to read it... gosh... it's way too hard for mi to understand that graph... i'm kinda confuse now >.<~

 

[echo47]

The Xilinx graph goes from 0 to 125 MHz.

The term "cut-off frequency" sometimes means different things to different people. Maybe he means "the -3dB point", but you should ask him to clarify.

The Xilinx graph's maximum amplitude is about 72dB, so -3dB is about 69dB, and that occurs at about x=0.49. Multiply by 125MHz to get 61.25 MHz.

Or you can use my larger graph2.gif. Its maximum amplitude is about 4100, so -3dB is about 2900, and that occurs at about 62 MHz.

 

[YenYu]

Wow, that's great. It clarifies my confusion. =)
Thx alot, it helps me lots with ur explaination.
Hmm... then is there any filter designing program u can recommend on? basically, the output of the waveform is going throught a passband filter onli. Which would work on my VHDL.

 

[echo47]

I use MATLAB for filter design. The optional "Filter Design Toolbox" is a big time-saver (for example, the freqz function that I used earlier). The optional "Filter Design HDL Coder" generates VHDL or Verilog code, however it's not area/speed optimized for any specific devices.
**broken link removed**

MATLAB is somewhat expensive, but students and schools get big discounts. I think it is the single most useful general-purpose engineering software. It is relatively easy to learn thanks to its excellent built-in help.

If you only need a tool that designs a specific kind of filter, I've seen several free programs floating around the web. Most tools give you only the filter coefficients, so it's up to you to implement the arithmetic. Try Google search for "filter design applet". Here's one example:
http://www.dsptutor.freeuk.com/

Hey! I just found a bunch of fun applets, including a digital filter. These are educational demonstrations, not practical design tools.
http://www.falstad.com/mathphysics.html

 

[YenYu]

Oh... thx for the recommendation of the sites...

Currently i guess i'll need a filter design that i could make which will down converts my waveform amplitude at the cut-off frequecy of the filter. But for this i'm not quite sure about the idea too... I'll ask my supervisor and provide it in more detail.

Well, even MatLab give great discount to students but it's still a price which most student cant afford it...

I've seen MatLab in other labs of my sch. But it is not accessible to any student. So it's kinda hard for mi to use MatLab to help mi in my filter design.

But still thx a bunch! =)

 

[echo47]

I have past experience with the starving-student syndrome.

Here are links to several free MATLAB clones and various toolboxes (including filter design). I haven't tried them.
https://www.dspguru.com/sw/opendsp/mathclo2.htm

They sure are small! SciLab is a 13 MB download. My MATLAB folder is over 1 GB.

 

[YenYu]

Wow.... u're Matlab is huge...
Alrite, I'll try some of the MatLabs to see which suits me best.

Thx alot bro! ^^

Added after 2 hours 45 minutes:

Help! Need an Urgent reply.

here's my problem now. With using different output frequency from my DDS, i should get different frequency of my waveform. But when using frequency which is higher then the cut-off frequency, which is from 61.26MHz, my amplitude of my output doesnt decrease. Let's say... i wanna get a 75MHz output waveform, i would use 125MHz-50MHz(DDS Output)=75MHz. 75MHz is higher then the cut-off frequency, the amplitude of the waveform should drop.

1stly, the amplitude i get from the ModelSim is in decimal, how should tally it with the magnitude response graph?

2ndly, how do u explain the normalise frequency (x pi rad/sample) ? What does it stand for in that graph? i mean how should i explain this in my presentation? My supervisor question mi on this.

3rdly, wat is the meaning of "Efficiency of Mechanization", used in adv way.

Added after 37 minutes:

At X = 1.0,
(1.0*pi radians/sample) * (250M samples/second) / (2*pi radians/cycle) = 125M cycles/second = 125 MHz

Where did u get the 2*pi radians/cycle from?

 

[echo47]

Looking again at ModelSim, your filters seem to be clocked at 500 MHz, not 250 MHz. I'm confused! That would affect our past discussions about cutoff frequency.

I don't yet have a clear picture of your overall system design. Do you have a block diagram showing the various inputs, outputs, mixers, filters, frequencies, sample rates, number of data bits, etc?

When you mix 125 MHz with 50 MHz, you get both 75 MHz and 175 MHz. Are you using the filter to extract the lower frequency component? Did you say your filter sample rate is 250 MHz? That would cause anything greater than 125 MHz to be aliased downward in frequency. That could be causing your unexpected high amplitude output from the filter. (I have not closely examined your filter behavior in ModelSim.)

The filter graphs show gain versus frequency. For example, if the gain at a particular frequency is about 4100 (+72 dB), and if the filter input amplitude is 511/2 (the mixer output's low frequency component), then the filter's output amplitude should be about 1047550. Indeed, I see about 1047100 in ModelSim.

(x pi rad/sample)
Those are units of frequency. Frequency is angular change per time interval. Instead of the familiar "x cycles per second", you have "x pi radians per sample". "Cycles" and "pi radians" both describe an angular change. "Second" and "sample" both describe a time interval.

(2*pi radians/cycle)
That's a simple conversion constant. There are 2*pi radians in one sinewave cycle.

"Efficiency of Mechanization"
??? That sounds like something from mechanical engineering or factory automation.

 

[YenYu]

Looking again at ModelSim, your filters seem to be clocked at 500 MHz, not 250 MHz. I'm confused! That would affect our past discussions about cutoff frequency.

If u check the coregen, it is clocked at 250MHz.

I don't yet have a clear picture of your overall system design. Do you have a block diagram showing the various inputs, outputs, mixers, filters, frequencies, sample rates, number of data bits, etc?

I've haf attach my presentation slide and report on my down-coverter. So u might haf a clear picture from there.

The filter graphs show gain versus frequency. For example, if the gain at a particular frequency is about 4100 (+72 dB), and if the filter input amplitude is 511/2 (the mixer output's low frequency component), then the filter's output amplitude should be about 1047550. Indeed, I see about 1047100 in ModelSim.

How did u manage to know it should be about 1047550? Does 1047100 correct of the modelsim interpretation?

"Efficiency of Mechanization" - I read it on the data sheet of the FIR filter. I've also attach it together with the reports. Not very sure... but it is used in an advantage way. I've look around the web but i did not manage to get the idea of wat is it.

 

[YenYu]

Hmm, this might be a dumb question but i had to ask.
Let's say, wat if some one asked u : "What is a CoreGen?"
How would u answer? I onli know the functions of a Coregen.

 

[echo47]

"If u check the coregen, it is clocked at 250MHz"
No, that setting tells coregen the clock frequency that you intend to apply to the core. Your HDL needs to somehow generate a 250 MHz clock and connect it to the core. As an alternative, you could clock the filter at 500 MHz, and enable it on every other clock cycle, assuming the filter core provides a clock enable input. (The enable method would eliminate the need to design critical timing logic necessary to reliably interface between a 500 MHz clock domain and a 250 MHz clock domain.)

However, with the filter running at half-speed, you may encounter other problems due to aliasing the mixer's high-frequency component down into your passband. Why did you plan to clock the filter at 250 MHz instead of 500 MHz?

Earlier I said, "... that could be causing your unexpected high amplitude output from the filter". No, the actual reason for the unexpected high amplitude is simply because the filter is being clocked at 500 MHz instead of 250 MHz, so its cutoff frequency is twice as high.

"How did u manage to know it should be about 1047550?"
Input_amplitude * gain = output_amplitude
511/2 * 4100 = 1047550

"Does 1047100 correct of the modelsim interpretation?"
Unclear -- missing words?

"Efficiency of Mechanization"
I guess that's just a strange way to say "easy to implement". The document explains how distributed arithmetic is easy to implement in FPGA logic fabric.

Coregen is short for "core generator". It's a software utility that generates a module containing intellectual property (a "core") that can be customized by setting various parameters.

 

[YenYu]

Indeed, I see about 1047100 in ModelSim.

Is this "1047100" should be a correct answer? Because the value u've calculated and the value u haf seen is different.

However, with the filter running at half-speed, you may encounter other problems due to aliasing the mixer's high-frequency

I'm not sure, because i thought it's clocking rate is set at the coregen.
But i've try using another clock to clock my filter at 2ns which is 250MHz. But it gave a straight line '0' as the output of my it2 and qt2.

Alrite... Most of ur explaination gave mi good ideas on wat is it.

 

[echo47]

In ModelSim, the filter's output sinewave swings from about +1047xxx to -1047xxx. That approximately matches my prediction. The numbers vary slightly because the filter's frequency response isn't perfectly flat, and because the sinewave is quantized (not a smooth curve). What values do you see in ModelSim?

Coregen does not generate the filter's clock. You connected the 500 MHz clock to the filter in DownConverter.vhd. Look at the filter output waveform, and you will see it changing every 2ns, which means it is being clocked at 500 MHz.

Now that I better understand what the system is suppose to do, if you change the filter's clock to 250 MHz, you will probably get aliasing troubles, such as the I or Q output being a flat line due to signal cancellation. This sounds like a fundamental design flaw. I suggest leaving the filter clock at 500 MHz, and changing the filter coefficients so it cuts off around 62 MHz, or wherever you need it. However, 500 MHz may be too fast for the filter core in a Virtex-4.