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Code VHDL - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 entity ent1 is port ( a : in std_logic; b : out std_logic ); end entity ent1; architecture struct of ent1 is signal x : std_logic; component ent2 is port ( a : in std_logic; b : out std_logic ); end component ent2; component ent3 is port ( a : in std_logic; b : out std_logic ); end component ent3; begin u1 : ent2 port map ( a => a, b => x ); u2 : ent3 port map ( a => x, b => b ); end architecture struct;