HDL Cosimulation blocks in Simulink

[noura7]

hi

how can I configure the HDL Cosimulation blocks in Simulink connected together?

thanks

 

[TrickyDicky]

Thats a very broad question.
If you have 2 co-simulation blocks, you need to run two instances of modelsim (and therefor 2 licences)
Or you could write an HDL wrapper that instantiated both blocks and connects them inside the HDL.

 

[noura7]

you could write an HDL wrapper that instantiated both blocks and connects them inside the HDL.

what's mean that and how?

 

[TrickyDicky]

you write a wrapper file in VHDL or Verilog, and co-simulate the wrapper.

 

[noura7]

you mean "wrapper" file a one file!!!

 

[TrickyDicky]

your post makes no sense - could you ask more specific questions?

 

[noura7]

on a wrapper file = on a one file

 

[TrickyDicky]

Your posts make no sense.
A wrapper file is just an HDL file

 

[noura7]

sorry for that. I know HDL file that's mean VHDL or VERILG file. For the first time i hear about the word "wrapper" that's make confusion for me

 

[TrickyDicky]

A wrapper file is just an HDL file that wraps around 1 or more entities, mainly for connectivity reasons. All you do is instantiate the entites and connect them together

 

[noura7]

please can you give me an example (.v or.vhd) file

 

[TrickyDicky]

If you dont understand VHDL or how to instantiate components, I suggest you google a VHDL tutorial.

https://www.google.co.uk/search?q=V...s=org.mozilla:en-GB:official&client=firefox-a

 

[noura7]

no i can describe one component with vhdl or verilog language but one i have for example 4 components how can i instantiate and connected them together. Can you please give an file example to follow that thanks!

 

[TrickyDicky]

use signals to connect the ports:

---

Code VHDL - [expand]
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
entity ent1 is
  port (
    a : in  std_logic;
    b : out std_logic
  );
 end entity ent1;
  
architecture struct of ent1 is
  signal x : std_logic;  
  
  component ent2 is
    port (
      a : in  std_logic;
      b : out std_logic
    );
  end component ent2;
    
  component ent3 is
    port (
      a : in  std_logic;
      b : out std_logic
    );
  end component ent3;
    
begin
  
  u1 : ent2
  port map (
    a => a,
    b => x
  );
  
  u2 : ent3
  port map (
    a => x,
    b => b
  );
  
end architecture struct;

---