Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Galois field problem in Reed Solomon encoder in VHDL

Status
Not open for further replies.

ravipratap06

Newbie level 2
Joined
May 30, 2012
Messages
2
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,297
I'm working on the implementation of reed Solomon Encoder in VHDL. Can
you tell me how this block works?
The encoder is based on Galois field arithmetic where the 4 LUT blocks
are multiplied with 12,1,3,15.
We are giving input as 1 to 15(4 bit binary) to the multiplexer. The
control line is given as 1 at first. it is changed to 0 after all the
inputs have been provided.
So what will be the output after the control line is made zero in the
above block diagram?
 

Attachments

  • a.jpg
    a.jpg
    40.4 KB · Views: 98

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top