[SOLVED] defining a static value in vhdl

[ssc987]

hi..
i want to assign a static integer value to a variable and use that variable to store the integer in an array. in c language we have #define statement. is there anything as such in vhdl??
if yes then could u pls give me an example. my array is really long table of long integer values.

 

[permute]

look into:
constant x : integer := 5;
type int_array is array (natural range <>) of integer;
constant x_array : int_array(1 downto 0) := (1, 2);

also, modules can have "generics", which become constants within the entity, but can be passed in at instantiation.

a package can be included, which can be helpful for large arrays.

 

[lucbra]

short answer: No, VHDL has no such construct.
I don't see the point in defining a static in VHDL either. If you think of a testbench, then it's OK to use integers, otherwise, I would avoid it. VHDL is not intended for software, but hardware description, like the acronym explains:
VHSIC Hardware Description Language.

Arrays in hardware????

 

[permute]

There's nothing wrong with any of the above. the OP looks to be looking for declaring things as constants. In C, this is done either with a const variable, or using the pre-parser's #define. VHDL allows constants to be declared in an entity, package, or instantiation (generic). A constant array, even with very high level constructs, will usually synthesize just fine. eg, a constant array(0 to 511) of records containing fixed length strings, integers, ect... is just fine. Such might even be used with a function to allows a user defined ASM format to initialize a block ram.

Constant Arrays will usually infer ROMs or simple LUTs (depending on size), while non-constant arrays can infer RAMs. A key issue is resource sharing -- large RAMs/ROMs get mapped to the BRAM elements, which have a limited number of read/write ports. When more reads/writes (per cycle) are needed, the synthesizer needs to get creative, and at a minimum duplicate the ROMs/RAMs. In some cases, it will not use the BRAMs, but will use registers. In such a case the design will be very large.

 

[lucbra]

@Permute

Declaring a variable static in C is not the same as a constant in VHDL. A static can change value but retains it's value between function calls, a constant can't change value (similar in VHDL and C)!

The approach is much too academic. VHDL is intended to describe logic; nothing more, nothing less. If you define an array, at the end it becomes a chunk of RAM (distributed or block RAM).

 

[permute]

@lucbra
the OP gave the example using a #define, which would reduce to a constant at compile time.

 

[FvM]

@lucbra: It seems to me, that you have a narrowd view on programmable logic respectively VHDL capabilities. There is a whole world of arithmetic and signal processing behind basic logic applications, and they often utilize constants, arrays of numerical parameters and similar.

Because VHDL is missing a preprocessor, it can't understand #define statements that you can use in Verilog. But constants are an acceptable replacement for it.

 

[TrickyDicky]

hi..
i want to assign a static integer value to a variable and use that variable to store the integer in an array. in c language we have #define statement. is there anything as such in vhdl??
if yes then could u pls give me an example. my array is really long table of long integer values.

Do you mean you want to use 64bit integers? VHDL only supports 32bits integers in the integer type, but with unsigned/signed types you can have as many bits as you want.

 

[lucbra]

@FvM - maybe I have a narrowed view of PLD's (I'm only working 13 years in the FPGA business), but the OP asked "assign a static integer value to a variable". Both you and permute (with all respect) replied with a construct that synthesize to a constant.
And yes: #define also translates to a constant in C, but that was not the question IMHO

 

[TrickyDicky]

@FvM - maybe I have a narrowed view of PLD's (I'm only working 13 years in the FPGA business), but the OP asked "assign a static integer value to a variable". Both you and permute (with all respect) replied with a construct that synthesize to a constant.
And yes: #define also translates to a constant in C, but that was not the question IMHO

in c language we have #define statement. is there anything as such in vhdl??

 

[ssc987]

thank you all for your help.
now the problem is:

#define a 96000
#define b 86000

when i use this preprocessor it allows me to use a and b instead of the integers all the time. how is it possible in VHDL?? there is a long list of integers which i need to access at frequent intervals..
for example 12 integer values are to be accessed 70 times and in different sequence. writing a state machine with maybe 50-60 states is out of question right??

 

[FvM]

how is it possible in VHDL??

I think, I answered the question exactly.

But constants are an acceptable replacement for it.

@lucbra: I don't see much sense in discussion about terms. They are used partly different in HDL flavours without involving a particular function. E.g. a variable in VHDL isn't the same as a variable in Verilog. My "narrowed view" was not related to terms subleties but to this statement:

VHDL is intended to describe logic; nothing more, nothing less.

It's simply wrong, in my view.

Technically, the question involves two parts: Defining constants and assigning them to "variable" arrays. The OP didn't say, if the arrays are intended to be used as structured constants or assigned different values in operation. This is an interesting point as well, but I didn't want to guess about it. The constant construct can be used as a replacement for a #define. It can be assigned to "variable" (signal) objects, if intended.

I also doubt, if the operation indended by the OP can be effectively performed by FPGA hardware. In so far it's reasonable to mention the differences to C programming. But as long no details are given respectively asked, I restrict myself to suggest suitable language constructs for particular purposes.

 

[lucbra]

FvM: VHDL and Verilog were originally (when it was defined) intended to describe logic to replace ABEL and similar logic descriptions. Later came testbenches and other (eg analog) functionality. And when you write synthesizable VHDL, then it always translate to logic (or embedded DSP blocks) in FPGA, CPLD's.
Think about the construct
always@ (..) in Verilog and process (...) in VHDL. These translate to a flip-flop (or register if you want).

You might be right about the OP's question, and I agree with your last paragraph.

 

[TrickyDicky]

FvM: VHDL and Verilog were originally (when it was defined) intended to describe logic to replace ABEL and similar logic descriptions. Later came testbenches and other (eg analog) functionality. And when you write synthesizable VHDL, then it always translate to logic (or embedded DSP blocks) in FPGA, CPLD's.

VHDL was origionally intended to define both logic and models, otherwise there would have been no use for "wait for", "after" VHDL constructs, let alone any of the file IO and access types. They have never had a place in synthesis. They have been in since the beginning of VHDL.