small value FIR coefficients

[kaz1]

We have a FIR design that uses reloadable coefficients. We want to exploit side coefficients as they are small values (0 to +/- 7 or so).
We use a percentage of filter length as small values and use this percentage as generic so that at compile time the dsp mapping is not done for such coefficients.
For such percentage there is simple logic/adders to get multiplication results instead of DSP blocks.

There is no problem implementing all that except that there is some uncertainty of the range of these small values as coefficients are reloadable and may have different scaling.
I can expand the value range or shrink it but I thought may be someone has done it before and might have some ideas as to best way to tackle this in a more efficient way.

I cannot use any logic to detect max value, nor can I assume a specific bitwidth for small values as any logic will be run-time and dsps will be inferred.

 

[FvM]

FIR related comment:
Small coefficients mean large error in frequency response. Some applications may tolerate it.

Usually required FIR coefficient resolution is derived from filter performance spec. I presume you have verified that 4 bit coefficient resolution basically works for it.

FPGA related:
I presume it's a fast filter application that can't be serialized. So you are basically asking how to implement many N x M signed multipliers without inferring DSP blocks. My first assumption is that design compiler will do this as efficicient as possible.

 

[kaz1]

The filter coefficients are configurable from 10 to 16 bits signed. I am focused on side coefficients which will be very small values (as any low pass filter). Because the coefficients are reloadable the compiler maps all of them to dsp blocks. The idea is how to stop that on side coefficients. It is not hard to define the side coefficients and stop the mapping but their values need to be known by designer to implement additions. This causes uncertainty unless scaling is predefined (but is configurable).

 

[KlausST]

Hi,

what does "small coefficents" mean?
* that value of a coefficient is low
--> I don´t call a value of +/- 7 as low. For me it is something around zero, like 0.0001 or so. If the sum of all FIR coefficents is "1.000" then you get a unity gain on DC.
* or a low count of coefficents
--> then I don´t understand what a count of "-7" means.

Klaus

 

[kaz1]

That is software approach about fractions. On FPGA there is no decimal point (for fixed point) .
I always read values as they are on the (bus) as integer. We all scale coefficients for hardware and then you may keep thinking of them as fractions or integers. I never use the concept of fractions on fpgas. If you look at fir compilers then you see options for integer coefficients (prescaled by you) or fraction(i.e. to be scaled by tool), I rather scale it myself. Moreover the final gain is the net effect of coefficient scaling and final sum truncation.