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Corners give you a digital dude's idea of what's "best" and "worst".
For analog, where any particular device and operating point could
be the one that matters, you'll learn very little from corners.
The problem with corners is everything matches. For analogue you usually want to know the effect of mismatches, so monte carlo is useful. I usually do corners as well to keep the digital guys happy! It doesn't take long compared to MC.
In addition, Monte Carlo gives you an idea of yield. Corners is much more extreme.
If you are really pushing the envelope, corners will give a too pessimistic result.
Corners determine the mean value, while monte-carlo gives the standard deviation.
There are 3 main types of corners, mainly PVT as you mentioned, of which you can trim only for process corners. So an example of a corner is NMOS FAST, PMOS SLOW, VDD=VDD(nom)*0.9 and T=-40C. To get the worst corner, you will need up to 2^N, or 16 corner runs in this example.
For MC analysis, the minimum run count depends on how many sigma you are designing for. Assuming the spec is normally distributed, 3-sigma gives 99.7% lot yield. So a 3-sigma design needs a minimum of ~1000 MC runs.
If you want a design that can guarantee up to 3-sigma lot yield, an approximation is when the worst corner mean +/- 3 sigma must still fall within the valid spec range.
the latter, of course. it's accurate and you can even put the mismatch information in the simulation. it's rather slow, though.
the former is fast but can only give you a rough feeling about the extreme case, but can you really know which combination of the PVT is worst case? Especially considering the circuit's performance is not necessarily monotonous for the variation of PVT, it's theoretically a mission impossible. However, if you have some experiences and your circuits are not "bizzare", you would have the ability to guess which combination of the PVT may be the worst case.
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