shhrikant1
Member level 2
Hello All,
please see the question below -
There is a 1 bit input say - 'a'
at every raising clock the input concatenated with 'a' again
i.e. at raising clk output will be- 'a' & 'a'
at next rising clk the output will be 'a' & 'a' & 'a'
and so on ...
it means after 10 clock pulse the output will be a 10 bit data which has to be converted to integer & check the divisibility of the number by two.
can any one give me any hint or an algorithm to solve this .
Can we use any gate logic in this algorithm.
Please help its urgent
thanks again
please see the question below -
There is a 1 bit input say - 'a'
at every raising clock the input concatenated with 'a' again
i.e. at raising clk output will be- 'a' & 'a'
at next rising clk the output will be 'a' & 'a' & 'a'
and so on ...
it means after 10 clock pulse the output will be a 10 bit data which has to be converted to integer & check the divisibility of the number by two.
can any one give me any hint or an algorithm to solve this .
Can we use any gate logic in this algorithm.
Please help its urgent
thanks again