Can I do this in VHDL? Is there a better way?

[edamark]

Hi everyone.

I am writing VHDL to interface with an SPI ADC.
Data ready DRDY pulses LOW to indicate that another sample is ready. There are 8 channels at 16 bits, so 128 bits to be read.

The values of the ADC MODE and CLKDIV signals mean that we have 256 CLKs between DRDY pulses.

I started by implementing a state machine, kicked off when DRDY = LOW, but of course if I generate the SCLK in the state machine by toggling the signal I get an SCLK freq which is half the CLK frequency. This then means the next DRDY pulse arrives while SCLK is still reading bits.

Ideally I would want to use 128 pulses at the CLK frequency to generate SCLK. The simple question is, how do I do this?
The state machine is clocked on the rising edge.
I made another state machine which is clocked on the falling edge.
By generating signals in each state machine I gated the clock using both signals to avoid glitches.
It must be wrong, there has got to be a much more elegant way of achieving this and I will kick myself when I find out.
Help!

 

[TrickyDicky]

if you want to run the sclk at the same clk frequencty, either connect it to the clock, or have the system clock run at 2x the clk speed required

 

[edamark]

if you want to run the sclk at the same clk frequencty, either connect it to the clock, or have the system clock run at 2x the clk speed required

Thanks for the reply. The clk also goes to the ADC and controls the convert rate.
It originates from a DDS module, so I suppose I could generate double the freq I need, then halve it for the clk, then my SCLK could come from the state machine with no worries about glitches.

Thanks for the idea, I will give it a go.
Is there really no other way of generating X-number of pulses at CLK frequency? What would a clock enable do? I am using a Spartan 6 btw.