bandgap reference circuit (patent : US 6933770 B1)

[learning_curve]

View attachment BGAP_patent_architecture.pdf

Hello all,

I was having some problems understanding what M1 and RB are used for in the attached bandgap schematic.
I understand the rest of the circuitry.

In a typical bandgap circuit, the output of the opamp goes to a current mirror, and Vbg is taken at the output (Drain) of the current mirror.
In this patent, the output of opamp is driving a CS transistor whose load is RB, I do not understand how this circuit works.

Can anybody help me understand this.

 

[JoannesPaulus]

it is explained in the patent between eq.8 and eq. 11

 

[student_of_analog]

Thank you JoannesPaulus...
now I have trouble identifying positive feedback loop and negative feedback loop for this architecture.
So, just for analysis if I break the loop going to the + terminal of the opamp and I look at the loop
connected to the - terminal of the opamp, it looks like the loop connected to the - terminal has positive feedback...
but isn't this loop supposed to be negative feedback ?

 

[JoannesPaulus]

The feedback loop keeps (V+)-(V-)=0. If you write the Kirchhoff law for the current you can readily identify the negative feedback.

 

[student_of_analog]

Thank you, I was analysing it like this.

if V- increaes, error voltage (difference at opamp input decreases), therefore output of opamp decreases, therefore output of M1 increases
which means V- increases again --- > positive feedback. Isnt't this loop supposed to be having negative feedback since its feedback factor
will be greater than the feedback factor of the other loop with V+ terminal.

 

[JoannesPaulus]

Not exactly: when the output of the op-amp decreases, the current thru M1 increases and (V-) decreases...

 

[student_of_analog]

But since M1 is a Common source transistor, if its gate voltage (output of opamp) decreases the drain voltage should increase, this is what I understand.
So I dont understand why the drain voltage decreases.

Also, like you said if opamp output decreases, Vgs for the pmos increases, therefore more current flows, that should also result in V- voltage increasing, because V=I*R and VY has increased
because of more current flowing.

Is my understanding wrong ?

 

[JoannesPaulus]

When the current thru M1 increases, the voltage drops over RB, RA1 and RA2 increase. Therefore VY decreases.

 

[student_of_analog]

JoannesPaulus,

I am sorry, I am not able to understand how VY decreaes.
If voltage drops across RB, RA1 and RA2 increase then doesnt it mean that VY also increases. ?

 

[JoannesPaulus]

If Vout is the bandgap voltage (kind of fixed). An increase "dI" in the loop current "I" will increase the voltage across RB, RB*(I+dI). The voltage VY is VY=Vout-RB*I and will become VY=Vout-RB*(I+dI), i.e. a lower voltage.