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axi master controller

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Hi

i huv designed verilog code for single master and single slave for AMBA3 AXI
now i want to calculate latency and throughput for axi rtl code
will u plz help me?

dont use sms of short hand typing.. consider this as warning...

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I think you need to write a AXI bus monitor to analyze the latency and throughput , it can be a SV or verilog model!
 

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