DMA Controllers with two dedicated master interfaces & internal FIFOs.

[Liffs]

Why do some DMACs with two synchronous and dedicated (not shared with CPU) AHB MASTER interfaces uses internal FIFOs? E.g.: ARM's PL080 has a 4-word internal FIFO... what's the big advantage of that?

 

[SynthWorks]

You would want to look at the part/board to see if the FIFO is for data or DMAC setup.


WRT data, the DMAC is reading from one interface and writing to the other. If the writing interface stalls, the read can complete a couple of operations before it stalls. They must be confident the busses are well balanced as I would expect the FIFO to be larger.

WRT DMAC setup, you could be queueing up the next operation in a FIFO as well.

 

[Liffs]

You would want to look at the part/board to see if the FIFO is for data or DMAC setup.


WRT data, the DMAC is reading from one interface and writing to the other. If the writing interface stalls, the read can complete a couple of operations before it stalls. They must be confident the busses are well balanced as I would expect the FIFO to be larger.

WRT DMAC setup, you could be queueing up the next operation in a FIFO as well.

The FIFO is meant for data.

I think it makes more difference when the data transfer is going from a fast "device" to a slow "device" than the other way around... after doing some (several) waveforms sketches I think I got the idea.

Just don't know which approach to use to set the FIFO depth.