Any Ideas for this FSM Design!!!!!!

[EEEngineer]

Hello ,

Here is what I would like to do for the incoming Bit stream of 0's and 1's.

The moment I see '01' I need to jump (or skip) the next incoming 45 bits and check if the next 3 bits are '1'. If yes then I need to print a "Success" message.

Could anyone please tell me if its possible for me to jump (or skip) 45 bits and check the next 3 bits.. I tried using #45 and wait(45) functions in verilog but doesnt work....or is it that I need to traverse through bit-by-bit 45 times till I reach those 3-bits.

Eg: Consider a sample Bit-stream:

00011 01 000101 00000000000000000000000000000001 1110001 1 1 1

After the first '01' , 45-bits should be skipped to check the 48, 49 and 50th bits for a '1' . If yes then "success" message is printed else "error"


Thanx,
waiting...

 

[li xiaomin]

define a counter, count down from 44, when output equal to 0, then....

 

[MWind]

What language are you using? In VHDL I would create a 3 state FSM using a typical FSM format. The first state would be to identify the "01" pattern. The second state would initiate a counter which would count the number of bits to skip. The third state would be to compare/capture the following bits. The whole FSM needs to be done in sync with the incoming bitstream clock.

 

[leonyang]

In my point of view, using counter is a good choice! How to implement the FSM depends on your favariate. The most important thing is that FSM must synchronize with the incoming bitstream.