Address decoder - misaligned

[jamesportman]

Hi,
I understand parts but getting confused, hopefully someone can help.

I have a CPU which needs the ROM to be sat starting at 0x2000, but the ROM is 0x8000 long, so it is misaligned, mounted from 0x2000 to 0x9FFF.
There is also a RAM chip which needs to sit at 0x0000 and is 0x400 size which is easy to sort.
If the ROM was sat at 0x0000, or 0x8000 say then it would be easy, the fact it is misaligned compared to its size is the issue.

I have seen loads of guides for straightforward setups but this seems more complicated.
It is all working in an existing circuit with some unknown IC doing the magic, which is possibly a PLD or similar.
It is literally taking 0x2000 away from the address on the CPU/bus and passing it through to the ROM perfectly. 0x2000 is 0x0000 on the ROM address pins, 0x4000 is 0x2000, etc.

It is also managing the chip enables depending on the incoming address ranges, read vs write on the RAM,
also the bus is 8 bit data/16 bit address multiplexed, so it latches the address using ALE pin from CPU, there is also RD and WE pins on the CPU to help with this.

I figured I might manage with normal methods but on top of decoding, would end up needing to fix the address by subtracting 0x2000, which isn't straighforward, or is it?

Am I going to be better off just using a PLD or similar to achieve this?

Photo of existing board, the header pins go to CPU/mainboard.
Thanks,
James

 

[nand_gates]

In your case for unaligned address you not only need to decode upper address bits CPU_ADDR[15:13] to generate
the chip select CS but also you need to generate ROM_ADDR[14:13] as follows...

CPU_ADDR[15:13]	ROM_ADDR[14:13]	ROM_CS
3'b001	2'b00	1
3'b010	2'b01	1
3'b011	2'b10	1
3'b100	2'b11	1
3'bxxx	2'bxx	0

 

[dick_freebird]

Back in the day when processors were either built from slices,
or too coarse a gate length to embed the function, you could
find MMUs (memory management unit) parts that you could
assign such mapping.

Whether any survive today, and at useful speeds / bus widths,
I dunno.

 

[FvM]

also you need to generate ROM_ADDR[14:13]

Not necessarily. Flash can be preprogrammed with rotated bank order.

 

[jamesportman]

Back in the day when processors were either built from slices,
or too coarse a gate length to embed the function, you could
find MMUs (memory management unit) parts that you could
assign such mapping.

Whether any survive today, and at useful speeds / bus widths,
I dunno.

Thanks I will have a look at those

--- Updated Mar 2, 2022 ---

Not necessarily. Flash can be preprogrammed with rotated bank order.

I specifically don't want to have to do that, the data on ROM needs to end up in the correct order for when people read/write to it in future in a separate eeprom programmer