Memory addressing and capacity

[engr_joni_ee]

Hi, my question is regarding this memory chip which is mt41k256m16tw-107-it. I guess this is 4 Giga bits memory or in other words it is 512 Mega bytes, right ?

MT41K256M16TW-107 IT datasheet and parts catalog

Discover all you need to know about Micron's MT41K256M16TW-107 IT DDR3 with product specs, downloadable datasheets, and more.

www.micron.com

I just have seen in one schematic, see attachment that the addressing pins are from A0 to A14 and the data pins are 16 (D0 to D15). With 15 bit addressing how can we have 512 Mega bytes ?

What if only A0 to A12 are connected to the FPGA and T3 and T7 which are A13 and A14 are not connected.

How much memory in Mega bytes we still can have with address pins A0 to A12 ? I am not sure how the Banks need to include in calculations.

 

[FvM]

Dynamic RAM uses multiplexed row and column addresses. Read the datasheet.

 

[engr_joni_ee]

If A13 and A14 are not connected then how much memory in Mega bytes one can have with addressing A0 to A12 connected to custom FPGA development board ?

 

[FvM]

You can't leave any address or control line floating, except for unused A15. Fixed level for A[14:13] gives 1/4 memory capacity.

https://www.mouser.de/datasheet/2/671/4Gb_DDR3L-1283964.pdf

 

[engr_joni_ee]

Do you mean that the same address A [0:14] is used for row and the same address is used for column ?

2 ^ 10 = 1 Kilo
2 ^ 20 = 1 Mega
2 ^ 30 = 1 Giga

I think I am getting it now for the memory MT41K256M16 - 32 Meg x 16 x 8 banks

Row Address: A[14:0]
Bank Address: BA[2:0]
Column address: A[9:0]

Which are 15 + 3+ 10 = 18 address lines and they can address up to 256 Mega locations, right ? and each location has 16 bit data so that makes 512 Mega Byte, right ?