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I don't know how other people do it, but if I want a
lot of delay I will add a shunt MOS cap after the first
stage (min N, equal drive P) and a couple or three
inverter stages to square it back up. If I want a more
controlled delay (and large) I might use a RC network
instead of depending on the first stage's drive current
to set timing (MOS very sensitive to Vdd, temp, process
while Rs and Cs tend to be 10-20% type tolerances).
I don't know how other people do it, but if I want a
lot of delay I will add a shunt MOS cap after the first
stage (min N, equal drive P) and a couple or three
inverter stages to square it back up. If I want a more
controlled delay (and large) I might use a RC network
instead of depending on the first stage's drive current
to set timing (MOS very sensitive to Vdd, temp, process
while Rs and Cs tend to be 10-20% type tolerances).
digital delay cells are not built like that. they are essentially a buffer, but the transistor sizing is such that one stage sees a big load. that is how delay is created. then the output is tweaked with the output stage to look like it switches relatively fast and delayed.
digital delay cells are not built like that. they are essentially a buffer, but the transistor sizing is such that one stage sees a big load. that is how delay is created. then the output is tweaked with the output stage to look like it switches relatively fast and delayed.
you are confusing delay with transition. a cell can have a huge delay, but the outputs might still switch very fast. think of a cell with multiple stages. the delay is proportional to the number of stages. the transition is proportional to the output stage driving capability.
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