Open Source digital design from scratch

[dick_freebird]

I am being asked to quote an ASIC design which contains
(per customer) about 1500 gates of 30-year-old standard
cell logic. The design team are fled or dead, nobody can find
anything about the crusty old cell library and only paper
schematics exist. No electronic-format design data at all.

Does anyone here have experience standing up not just
the routable netlist from schematics, but the views that a
logic synthesis would demand? Perhaps has found some
"full design flow" tutorials (I am with a fab that does none
of this themselves, but wants to print the part).

I am imagining some light reverse engineering to find
the gates' internal W and L, timing simulations using the
old foundry models, populate verilog (or veriloga) models
depending on whether xschem can deal with netlisting
veriloga, and then gotta find somebody who's hep to that
autorouter jive. Which one, no idea. I haven't done anything
digital in decades and the last one was so close to the
bone that it had to be entirely hand crafted, the standard
cell library there could not even self-toggle at main clock
freq. So all done analog style, 10Kgates and a few thousand
vectors' worth run through Spectre.

I am not looking to repeat that experience. What's the lowdown
these days on getting it done from scratch with open source
tools?

 

[ThisIsNotSam]

you are looking at a steep hill. open source tools can do synthesis and even some digital layout of acceptable quality if you have RTL, which you don't.
if you had a netlist from library A and wanted to migrate to library B, that is possible with some tinkering, but then again you don't have a netlist.
for the whole reverse engineering part of your problem, no tool that I am aware of can do it. as in, take a hand drawn schematic and build a readable file format out of it.

I think the easiest way to approach the problem would be to hire someone to rewrite RTL. then you do whatever you want with it afterwards, using commercial or open source tools