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coding standard - explicit bus width in all assignments?

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nachumk

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I have recently run across this Verilog coding standard:

Use explicit bus widths during assignments, connections, and reads:

reg [7:0] data;

always @ ...
data[7:0] <= ...

case (state[1:0])
...

mod mod_inst (
.d(data[7:0]),
...
);

I have serious issues with this, but I'm curious what others think.

Thanx,
Nachum
 

it seems a bit unnecessary, but can be helpful. It makes the user confirm that the connections are the correct width. I don't think many people will go through the hassle though.

My guess is that the code comes from someone who learned verilog this way, or took it from code samples.

A third possibility is that the code was auto-generated by a script. is that case, there might be a function that automatically expands the ranges when printing the code.
 

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