nachumk
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I have recently run across this Verilog coding standard:
Use explicit bus widths during assignments, connections, and reads:
reg [7:0] data;
always @ ...
data[7:0] <= ...
case (state[1:0])
...
mod mod_inst (
.d(data[7:0]),
...
);
I have serious issues with this, but I'm curious what others think.
Thanx,
Nachum
Use explicit bus widths during assignments, connections, and reads:
reg [7:0] data;
always @ ...
data[7:0] <= ...
case (state[1:0])
...
mod mod_inst (
.d(data[7:0]),
...
);
I have serious issues with this, but I'm curious what others think.
Thanx,
Nachum