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do you know why I get
# Error: ELAB1_0021: filename.vhd : (lines, 0): Types do not match for port "some_port".
Aldec FAQ says:
If you are receiving this error, please check which standard you are using when compiling your files. If you are using different standards for different files, (e.g. 2002 and 2008) this error can occur. You will need to compile your files using the same standard.
But I don't understand what it means, like i looked for on tool>perferences and it shows VHDL compiler- standard version- VHDL 1076-2002. But this is the setting I am using for compiling all the vhd files in my project. so the possible reason- "different standards for different files" would not apply to me! or is it?
what I mean is - both numeric_std and std_logic arith define the types unsigned and signed. If you had ports of type signed or unsigned, and one file used std_logic_arith while the other used numeric_std, then you may get a missmatch.
PS. std_logic_arith and std_logic_unsigned are not standard VHDL libraries.
thanks, you are right
i changed from std_logic_arith to numeric_std and solved two port mismatch, however another port is showing mismatch and i am looking at this
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