Binome
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Hi,
I'd like to generate pseudo-random numbers in my synthesizable VHDL design. I've found this code : https://github.com/jorisvr/vhdl_prng/blob/master/rtl/rng_xoroshiro128plus.vhdl and it looks great but the seed is stuck to zero in the top-level component. I would like the seed to be different each time I run the design. Is there a way (maybe the time, the temperature,...) ?
I'd like to generate pseudo-random numbers in my synthesizable VHDL design. I've found this code : https://github.com/jorisvr/vhdl_prng/blob/master/rtl/rng_xoroshiro128plus.vhdl and it looks great but the seed is stuck to zero in the top-level component. I would like the seed to be different each time I run the design. Is there a way (maybe the time, the temperature,...) ?