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Recent content by vsrpkumar

  1. V

    Regarding design related to power intent

    Hi, I am trying to learn CPF format. Can anyone give a specification for the design which has retenation,always-on, isolation cells. I want to know these stuff from designers perspective. I don't need RTL coding but just specification at the block level for concepts. My mail id is...
  2. V

    question in synthesis

    good question of synthesis Dear Friends, I attended interview.I was asked this questions.I cleared interview but some of them i was unable to answer.Kindly answers for this questions. 1) what are advantages and disadvantages of TOP-Down and Down top synthesis Approach 2) What is...
  3. V

    query in gated clocks

    Is gated clocks verified by DC formailty.I am using gated clock with AND gate and enable signal synchronised in the negative edge of the clock.How to verify in DC formality.Thanking you Kumar
  4. V

    How to display the frequencies and the pulse width of DUT clocks using Verilog?

    I am writing test bench for a DUT.In that DUT there is clock generation unit(sub block) with dividers and mutilpiers What i want is there any method to display the frequencies and the and the pulse widths of the clocks(some are gated clocks) in prompt display .I dont want to see the simvision...
  5. V

    query in byte blaster/signal topic logic analyser

    Dear All. I want to see the signals in the EP2C12Q240C8 FPGA for my design inside with several instances..It has EPCS4 configuration device .I am using quartus7.1 s/w.I am using byte blaster II download cable.I am using LVTTL standards for all I/O with VCCINT 1.8V VCCI/O 3.3V.Which...
  6. V

    Can I simulate a Verilog IP core and C application code in Cadence environment?

    I am prototyping a IP core which was written in verilog languge in cyclone II FPGA.My application engineer wrote code in C for application level.Can i simulate the both in cadence simulation environment so that i can find the bug in real environment .Can anyone suggest on this.I am in desperate...
  7. V

    Doubt in Design compiler

    I am novice to design compiler This is statement in design compiler Ideal network propagation can traverse combinational cells, but it stops at sequential cells, even if the sequential cells are connected to ideal clock pins. I have this doubts 1) If a combination circuit has two inputs,one...
  8. V

    The timing in a latch based design

    Re: Latch based design I am too searching for good material for latch based design and their timing.
  9. V

    What are the precautions for constraining latches in RTL coding?

    I am new to Design compiler.My entire core works on a system clock .but for external communication I am using I2C bus(asyncronous logic) with help of latches for communication between system clock and I2C bus.How to constrain latches.Generally what precaution should be takes for latches while...
  10. V

    Discrepancy in flipflop regarding clock cycle

    1)my doubt in flipflop is the output of flipflop comes in next clock cycle when the data samples in previous clock cycle(simulation case) But in practical case if tpclk->Q is zero the output comes immediate. Why this discrepancy. 2)what is difference between event based simulation and cycle...
  11. V

    query in limit cycle effect

    I am implementing IIR Filter in verilog with equation y(n)=a*x(n)+(1-a)*y(n-1) a is floating point no with 5 bits x is integer with 7 bit input .y(n) is 12 bit with 5bits floating and 7 bit integer part I used 2's complement logic for 1-a. I did multiplication by shit...
  12. V

    Can I simulate Verilog and C code simultaneously ??

    query in simulation I designed a first order IIR filter in verilog with floating point coefficients.I am writing equivalent C code.What my doubt is is it possible to simulate both verilog and C code simultaneously with the test vectors defined in verilog test bench.I think there will be...
  13. V

    query in analog to digital transformation

    I want difference between bilinear transformation and impulse invariant transformation.What is the difference between them in applicationwise
  14. V

    What is the difference between inertial and transport delay?

    !) what is difference between inertial and transport delay 2)what is register duplication and what is its use
  15. V

    How to calculate minimum skew and proceed with duty cycle other than 50% in STA?

    I am attachning a good material in sta My doubts are 1) in page 16.How to calculate minimum skew 2)in page 35 how to proceed with the duty cycle other than 50% Thanking you kumar
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