Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

query in gated clocks

Status
Not open for further replies.

vsrpkumar

Member level 4
Member level 4
Joined
Mar 26, 2006
Messages
74
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,286
Activity points
1,830
Is gated clocks verified by DC formailty.I am using gated clock with AND gate and enable signal synchronised in the negative edge of the clock.How to verify in DC formality.Thanking you
Kumar
 

clock gating logic is always a good way to save power.
in formality setup, set verification_clock_gate_hold_mode any

hope it helps

vsrpkumar said:
Is gated clocks verified by DC formailty.I am using gated clock with AND gate and enable signal synchronised in the negative edge of the clock.How to verify in DC formality.Thanking you
Kumar
 

Hey, this is another suggestion, from ur DC save a svf script and later read it using formality. These changes will be accepted by formality
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top