Alexxk
Junior Member level 3
Hello fellow chipdesigners 
I am a PhD Student working at a circuit design department that normaly only does analog stuff. I learned all the digital workflow stuff myself with free resources online and till now everything has worked. You can imagine though that a lot of know-how is missing. Now I want to add a gated clock to digital design. I have a clock coming from off-chip, and a shift reigster that I load with the enable information for 100 processing blocks. The indivudual clocks are simply AND combined from this enable signals (they can be assumed as static so to say, they will only be canged when the clock is not running).
My question now is: do I have to change my workflow? Does genus and innovus recognize that this is a gated clock and will still do the clock tree synthesis? because the clock signal I constrain with SDC constraints is actually only going to the 100 and-gates....
I put the design true genus and it doesnt see any gated clocks. Report_clock shows that my input clock still goes to the same number of register as before I introduced the clock gating code.
Thank you fot your help!
I am a PhD Student working at a circuit design department that normaly only does analog stuff. I learned all the digital workflow stuff myself with free resources online and till now everything has worked. You can imagine though that a lot of know-how is missing. Now I want to add a gated clock to digital design. I have a clock coming from off-chip, and a shift reigster that I load with the enable information for 100 processing blocks. The indivudual clocks are simply AND combined from this enable signals (they can be assumed as static so to say, they will only be canged when the clock is not running).
My question now is: do I have to change my workflow? Does genus and innovus recognize that this is a gated clock and will still do the clock tree synthesis? because the clock signal I constrain with SDC constraints is actually only going to the 100 and-gates....
I put the design true genus and it doesnt see any gated clocks. Report_clock shows that my input clock still goes to the same number of register as before I introduced the clock gating code.
Thank you fot your help!
