Discrepancy in flipflop regarding clock cycle

[vsrpkumar]

1)my doubt in flipflop is the output of flipflop comes in next clock cycle when the data samples in previous clock cycle(simulation case)
But in practical case if tpclk->Q is zero the output comes immediate.
Why this discrepancy.
2)what is difference between event based simulation and cycle based simulation
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[manenef]

Re: doubt in flipflop

Hello
with a flipflop it can either be edge triggered or level triggered.with edge triggered, this can either be in the positive edge or negative edge, and in that case there will be a delay of the output. this can lead to some difference in results.

kind rgds
manenef

 

[sekapr]

Re: doubt in flipflop

clk->q delay will never be zero.

Added after 25 seconds:

clk->q delay will never be zero.