Can I simulate a Verilog IP core and C application code in Cadence environment?

[vsrpkumar]

I am prototyping a IP core which was written in verilog languge in cyclone II FPGA.My application engineer wrote code in C for application level.Can i simulate the both in cadence simulation environment so that i can find the bug in real environment .Can anyone suggest on this.I am in desperate situation.Please help me.
Thanking you kumar

 

[kishore2k4]

Re: cosimulation query

If the code that was written runs on the IP core(like in the case of soft-cores) then just fill in the block RAMs in your FPGA and then simulate the whole thing.