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Recent content by VINAY_RAO

  1. V

    How to measure Bandwidth and Q of high-pass T-match circuit?

    Hello capcas, Thanks for your reply. Yes it is high pass filter. What i defined "B.W = (fr/Q)" is one of the definition of Q. I designed this circuit for Q=5. How can i measure resulted Q from the simulation plot? For high pass, i have to measure cut-off frequency and then i got to find out 'Q'...
  2. V

    Problem to Run Monte Carlo Simulation in ADE XL

    The following link may help you to resolve. https://www.cadence.com/Community/forums/p/13377/20678.aspx Regards, Vinay Rao.
  3. V

    Help to understand measurement of Q, Bandwidth and T-match behavior

    Hello all, Can any one help regarding my two threads. Here are the following link to those threads. https://www.edaboard.com/threads/244365/ https://www.edaboard.com/threads/244300/ Any ones help would be greatly appreciable. Thank you. Regards, Vinay Rao.
  4. V

    How to measure Bandwidth and Q of high-pass T-match circuit?

    Hello all, Here I attached the circuit and dB plots of its S11, S21 and ZM1. I designed this circuit for fr (center freq/resonating freq) =2.4GHz and Q = 5. From theoretical concept, I am calculating Bandwidth as B.W = (fr/Q) = 480MHz. How can I measure simulated Bandwidth and Q from the plot...
  5. V

    How to interpret T-match behavior?

    Hello vfone, Thanks for your reply. My doubts are not cleared rather got into many. I agree to the fact that any independent energy storage elements with R give poles. But in my circuit, 1> How can I find how many independent energy storage elements are present to get poles (here 2 cap &...
  6. V

    How to interpret T-match behavior?

    Hello all, I have designed the T-match network to get resultant impedance of 2 Ohm out of 50 ohm load. I have plotted S11 & ZM (both mag & phase) and getting exact results (I have attached both circuits and simulated results). But one question is popping up in my mind about its behavior. I take...
  7. V

    Difference between N/P –select and n/p - active layers in CMOS layout techniques

    Hi, What is the significance of using n/p select layers along with n/p active layers to make a CMOS active device? Why we need to draw extra n/p select layers though we can distinguish P and N regions just by using P/N active regions? Regards, Vinay Rao.
  8. V

    Materials for RF CMOS CKT Design

    Hi, I am new to RF design and want to start off with it. I want to know about-- 1)Are there any video lectures available on RF CMOS CIRCUIT DESIGN? 2)Which book is preferred ? (is RF Microelectronics by Razavi ok?) 3)Any university link which has got the best material? (I got TAMU's material...
  9. V

    Simulating DAC or ADC in cadence

    hi,, I am using ic5141 and wrote a simple verilog-ams code for 1-bit DAC where input is digital signal and output is analog.After that i instantiated in schematic window for simulating it. I reffered manuels to simulate this but i am not getting any proper idea for simulating mixed design. For...
  10. V

    About behavior modelling of ADC

    In behavior modelling of flash ADC,by simulating the idea of architecture ,is it possible to predict the resulting sampling frequency of the ADC???. We need to include real time delays while simulating to anticipate the sampling rate for the architecture we selected??
  11. V

    TSMC 60nm or 45nm technology foundry file(spectre & spic

    hi, Any one has got TSMC 60nm or 45nm technology foundry file(spectre & spice)?? Pl reply, Thank you..
  12. V

    Future work in FINFET modelling

    hi, I would like to work in modelling of FINFETS , does any one knows about the future works of FINFET modelling ???..
  13. V

    problem in running IC610 (CADENCE)

    i used virtuoso only,,and i run with only .cshrc file where i wasnt having any .cdenv or .cdinit file.Even after running,in current working directory its nt storing default .cdenv files,even i checked whether it is hidden,but its not hidden.. how can i check in .cdenv file??
  14. V

    problem in running IC610 (CADENCE)

    Hi, Recently i installed IC610 (cadence),but while running "icfb" i am getting many errors.When i give the comand "icfb" ,CIW opens but in between it ask for :"(delicense-7) couldnt get a license for schematics L.would you like to try to get a higherr tiered license to run this...
  15. V

    Abt CADENCE VERILOG-XL PROBLEM

    HI, I am facing many problems while openening VERILOG-XL in CADENCE.If i am going to V-XL through schematic (as tool-simulation-verilog-xl-setup enironment-run directory(ex:mos.run1)) after setup env's ok ,its showing the error as "INVALID VERILOG EXECUTABLE VERILOG,Please check existance...
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