VINAY_RAO
Junior Member level 2
HI,
I am facing many problems while openening VERILOG-XL in CADENCE.If i am going to V-XL through schematic (as tool-simulation-verilog-xl-setup enironment-run directory(ex:mos.run1)) after setup env's ok ,its showing the error as "INVALID VERILOG EXECUTABLE VERILOG,Please check existance and for permissions and try again,relative path names are relative run directory"...If i clsose the simulation option warning then verilog-xl window is opening..after setng up the environment and start interactive(simulation) in between error is coming..That error is "user-settable variable:verilogsimbinary is invalid.,Relative path names are relative to run directory"..
simulation is gtng aborted.If i am opnng directly thru the CIW window its shwng the same prob..
Hw cn i solve this prob???.
Pl reply soon,,pl if u dnt know ,pl ask ur administrator and help me..i am runnng out of time in my project...Its my humble request..
Thank you..
I am facing many problems while openening VERILOG-XL in CADENCE.If i am going to V-XL through schematic (as tool-simulation-verilog-xl-setup enironment-run directory(ex:mos.run1)) after setup env's ok ,its showing the error as "INVALID VERILOG EXECUTABLE VERILOG,Please check existance and for permissions and try again,relative path names are relative run directory"...If i clsose the simulation option warning then verilog-xl window is opening..after setng up the environment and start interactive(simulation) in between error is coming..That error is "user-settable variable:verilogsimbinary is invalid.,Relative path names are relative to run directory"..
simulation is gtng aborted.If i am opnng directly thru the CIW window its shwng the same prob..
Hw cn i solve this prob???.
Pl reply soon,,pl if u dnt know ,pl ask ur administrator and help me..i am runnng out of time in my project...Its my humble request..
Thank you..