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Recent content by sruthikesh

  1. S

    how to make clock gating signal only be used with clock signals?

    Library specific clock gating module instantiations are available... If u have a synthesized netlist u can find clock gated modules in that netlist, just instantiate them in the design with ur specific enable signal where ever u need to make whole module clock gating or register clock...
  2. S

    hierarchical power report: sub-design consumes more power than top design

    why to add "If I added up the power of all the level-1, level-2 and level-3 sub modules"?? because all sum of level-2 modules is the power of level-1 top module, adding all level-1 sub modules gives u the total power of the design. so, no need of adding level-2 and level-3 sub modules power to...
  3. S

    Magic number for a worst slack (RTL fixes vs Synthesis tricks)

    Hi, Generally in synthesis due to clock jitter the clock period what is specified in synthesis might not be met. so, while doing synthesis give the clock constraint more than what u need. Suppose if u need a clock of 100MHz for ur design then give the clock period in synthesis as 110MHz so...
  4. S

    Need for generated clock

    Clocks are generated in DC to specify input and output port delays... ex: If we take an input it might have delay coming from the source. So, it is used to specify the estimated time taken to arrive at your module. hope this helped...
  5. S

    When Clock Gating is done why does the CLOCK has to be gated low

    What actually clock gating does is it turns off the transition in flip-flop. let me give an example: always@(posedge clk) if (reset) d<= 'b0; else d<= in ; in the above case there wont be any clock gating becoz when ever there is poedge on clock there is transition. always@(posedge clk) if...
  6. S

    When Clock Gating is done why does the CLOCK has to be gated low

    Hi dftrtl clock gating to be high or low depends on the way flip-flop edge is referred. If u write a flop with negedge of clock then u go for gated clock to high. When it is posedge of clock then clock gated will be low, in order to turn off the flip-flop. So, that there is no transition b/w...
  7. S

    How to find number of registers in a design?

    Hiii, In DC there is a command "report_clock_gating" with this u can find total no. of registers , clock gated registers nd un gated registers.....
  8. S

    verilog code for following circiut?? help me!!!!!!!

    Hiiii harinisas, If u cant see the output in waveform then there might be a combinational loop.... so checkout for these... > I will give an example if declare a,b as wire's let 'c' be some other variable... >> assign a = c & b ...
  9. S

    Best Verilog coding methods for power optimization...????

    what are the critical contraints that must be added to design compiler to have an effective synthesized netlist in terms of area,power.... I heard abt the UPF but i don't know the perfect use of it.... can anyone give me some example.... nd How to generate a UPF file with synopsys tools...???
  10. S

    Best Verilog coding methods for power optimization...????

    ya i knw abt clock gating but doing it by hand for the whole design is too time takin.... nd tools like synopsys does that....
  11. S

    Best Verilog coding methods for power optimization...????

    ok but clock gating is done by tools.... but is'nt there any thing v can do to reduce power... can u tell me wat is tool for analysis to find out which part of my design is takin much power....
  12. S

    Best Verilog coding methods for power optimization...????

    Hiiii, I'm not able to find good verilog coding techniques for power optimization... Can anyone pls post some links for power optimization.... Thanks in advance
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