rabbitwayne
Newbie level 3
Hi,
I have done a power estimation of my design in DC with power compiler and generated a power report in hierarchical way.
However, I feel strange that in the power report some of the sub-designs consume even more power than their top design.
For example, the Complex_ALU consumes even more total power than its top design fu5, and the RenameMapTable consumes
even more power than its top design Rename.
This makes no sense, right? I wonder why this happens? Thanks for your help!
Here are two snippets of my power report:
I have done a power estimation of my design in DC with power compiler and generated a power report in hierarchical way.
However, I feel strange that in the power report some of the sub-designs consume even more power than their top design.
For example, the Complex_ALU consumes even more total power than its top design fu5, and the RenameMapTable consumes
even more power than its top design Rename.
This makes no sense, right? I wonder why this happens? Thanks for your help!
Here are two snippets of my power report:
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