Magic number for a worst slack (RTL fixes vs Synthesis tricks)

[ivlsi]

Hi All,

Let's say I've synthesized my design and got some violated paths...

So, how would I determine whether they should be fixed by future netlist optimization or by RTL fixes?

Let's say I've got a worst slack of 10% of Clock Period (0.1*T)... Should I try to apply additional timing constraints and logic optimization techniques on the critical paths or should I go and fix my RTL structure?

If the slack was 15% of the Clock Period? 20%? 30%? ... 50%? What's the magic number when I should say "stop your synthesis tricks, go back and fix your RTL!".

Thank you!

 

[sruthikesh]

Hi,

Generally in synthesis due to clock jitter the clock period what is specified in synthesis might not be met.
so, while doing synthesis give the clock constraint more than what u need. Suppose if u need a clock of 100MHz for ur design then give the clock period in synthesis as 110MHz so, that after synthesis the clock achieved might be 100MHz.
Generally we give a clock of 10% more than what we need, this depends on the frequency what is needed for the design. Also this effects the area and power as frequency is increased.

Hope this is helpful.

 

[mail4idle2]

The thumb rule is You increase the clock frequency in synthesis by 20% to the frequency you have targeted for your module to work.

 

[ivlsi]

what about setup/hold uncertainty?

How should it chosen?

What about in/out delays? How should they be over-constrained?

BTW, I heard that over-constraining the design is a bad practice... What do you say?

 

[mail4idle2]

20% Reduction in clock period is not over contraining the design.
When you follow above line every thing is taken care.

 

[ivlsi]

while doing synthesis give the clock constraint more than what u need

Isn't better to define clock uncertainty ? It was actually introduced to model a jitter on the clock, isn't it?

Increasing of Clock Frequency will not cover hold variations (in my opinion).

 

[ivlsi]

Should setting of 20% uncertainty for the clock be equal to increasing the clock frequency by 20% ?