Best Verilog coding methods for power optimization...????

[sruthikesh]

Hiiii,

I'm not able to find good verilog coding techniques for power optimization...
Can anyone pls post some links for power optimization....



Thanks in advance

 

[nisshith]

I don't think that you can do much at RTL level in terms of power optimization.
Clock gating is the only technique i can think of to optimize design in terms of power at RTL level.
In order to study more about clock gating you can google it there is a large amount of study material easily available on net. like Clock gating - Wikipedia, the free encyclopedia

 

[sruthikesh]

ok but clock gating is done by tools....
but is'nt there any thing v can do to reduce power...
can u tell me wat is tool for analysis to find out which part of my design is takin much power....

 

[nisshith]

no u can code gated clock in verilog.
like

module DFF (Din, Q, CLK, EN)
input Din, EN, CLK;
wire gated_clk;
assign gated_clk= EN && CLK;
always @ (posedge gated_clk)
Begin
Q<=Din;
end

Above is a example of gated clock. The flip flop will only work when EN is "HIGH"

No there is no method to estimate power at RTL level.

 

[sruthikesh]

ya i knw abt clock gating but doing it by hand for the whole design is too time takin....
nd tools like synopsys does that....

 

[rca]

RTL code could not reduce power, but defining a better architecture of the system, reducing the number of flop to use, will help, adding data gating to reduce the combinational consumption....

 

[dave_59]

The UPF IEEE 1801 standard saves you from writing a lot of low level detail by creating power domains that can be globally applied to your RTL. Simulation tools from Mentor and Synopsys support this behavior as well as certain synthesis tools. See Questa Power Aware Simulator - Mentor Graphics and **broken link removed**

 

[sruthikesh]

what are the critical contraints that must be added to design compiler to have an effective synthesized netlist in terms of area,power....
I heard abt the UPF but i don't know the perfect use of it.... can anyone give me some example.... nd
How to generate a UPF file with synopsys tools...???

 

[rca]

upf (or cpf) is only here to define voltage island, isolation to add automatically bye the tool the required isolation cell, level shifter, power switch.
the power optimisation, could include gated clock insertion using HVT cells.

The power reduction imply, to have done first the architecture analyzis, before to be on the tool.

 

[oratie]

ya i knw abt clock gating but doing it by hand for the whole design is too time takin....
nd tools like synopsys does that....

Still, if you didn't describe clock gating in verilog (RTL), see example above, Synopsys will nothing insert. Synopsys is only replace such verilog descritpion by clock-gating cells.

 

[rca]

DC or RC could add gated clock when you do not have any gated clock already coded in your RTL code.
The tool moves the data gated condition to the clock.