how to make clock gating signal only be used with clock signals?

[quiet83]

I have a question about the signal used for clock gating.
Is there any command to make one signal only used for gating the clock but not be involved in generating the input signal for the register?
For example, I have added a signal to enable one register, if I use the clock gating, that enable signal will be used both for gating the clock and generating the input of the register. Is it possible to make it only used for gating the clock?
Thanks.

 

[Prashanthanilm]

Quiet83,

Command?.

Which language you are working in.

 

[quiet83]

i mean the command of design compiler

 

[sruthikesh]

Library specific clock gating module instantiations are available...
If u have a synthesized netlist u can find clock gated modules in that netlist, just instantiate them in the design with ur specific enable signal where ever u need to make whole module clock gating or register clock...