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Dear All,
I am designing a push-pull regulator for digital circuits. The schematic is as attached. It consists of pre-amplifier followed by comparators (push and pull side) and finally switched source-follower output stage (push and pull side). I have verified that all the feedback loop...
Hi All,
I have designed LDO with NMOS pass transistor with 35mV dropout (1V supply regulated down to 0.965V). Since the dropout voltage is small then my PSRR is bad (-38dB @dc and 0db @10MHz). Furthermore the NMOS pass transistor is sized in triode region (to get smaller device and small...
Hi All,
I am designing a push pull shunt regulator circuit for regulation of digital circuit. The block diagram is attached (PushPull_Block_Diagram.jpg). The circuit implementation is also attached (pull_up_schem.jpg --> for pull up function and pull_down_schem.jpg --> for pull down function)...
Thanks Erikl for correcting me.
Now I managed to get the regulation level and the regulator is stable @light load=1mA and also heavy load=50mA. As you can see from the attached loop gain sim results, @IL=50mA, Fu=250kHz, Phase=52Deg, Gain=50dB AND @IL=1mA, Fu=2MHz, Phase=69Deg, Gain=65dB. When...
Hi Erikl,
Can you explain little bit more on this?
I used the following equation to set my Vreg. (Please correct me if i'm wrong!). Vreg=(1+R2/R1)Vref and I set Vref=900mV and thus R1=3.6k and r2=50k. This is how I end up with only 6.7% of my output voltage.
Should I feedback 90% of output...
Thanks for the advice. I re-sized my power device using linear equation to get 700mOhm (35mV dropout). Rds(on)=700m=2L/(Kp*W)(VSG-VTH) and after few tweaking I end up with L=0.3um and W= 6004um (Not so big compared to my first design :)). The problem now is since the PMOS has to be in triode...
Hi All,
I attach the schematic (including dc node voltages) for LDO with two-stage OTA and PMOS power device. In order to get dropout voltage of 35mV, I used the following equation to size up the PMOS. W/L=(2Id)/(kp*vdssat2) and vdssat=35mV. I end up with a very huge PMOS, W/L=469153. The...
Hi All,
Is it possible to design LDO with dropout voltage of 50mV? The average load current is around 10mA and it can peaks as high as 50mA. The regulated voltage is to supply to digital circuit and VCO. I'm afraid that without regulation, the noise and current variations will degrade the...
You should break the loop at 'in2' node. As what erikl suggested, using LC method, you can put a big inductance (1kH) and big capacitor (100uF) and injected your ac test signal.
Hi All,
Thank you for your valuable feedback. Indeed as mentioned by steadymind and FvM, the culprit is due to incorrect bias because of pwl source is used to supply (2.5V) for the error amplifier. I should be using dc source instead. Now I can get correct loop gain (39dB) and phase margin...
Thanks LvW and FvM.
LvW,
I slightly modified my circuit as following:
The input current is set to 20mA--> Iin=(Vsupply-Vref)/Rseries=(1V-0.9V)/5ohm=20mA. Is this the correct method to design shunt regulator?
The maximum load current is set by the resistor (Rload=47ohm-->Iload_max=19mA)...
Hi lvW,
Hopefully the new attachment is more clearer. Yes, the graph is in negative -dB and that is why i said it looks strange. This is my first time designing shunt regulator and I was expecting the loop gain to be in positive dB and I don't have ideas how to measure phase margin from the...
Hi All,
When I simulated the loop gain and phase margin (See attached schem for sim setup), the simulation results look's strange. How to measure phase margin from the plot? Is the simulation result correct? If not, how to get the correct result?
Note: The circuit is shunt regulator and I did...
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