Is it possible to design LDO with max 50mV dropout voltage?

[sjamil02]

Hi All,

Is it possible to design LDO with dropout voltage of 50mV? The average load current is around 10mA and it can peaks as high as 50mA. The regulated voltage is to supply to digital circuit and VCO. I'm afraid that without regulation, the noise and current variations will degrade the digital circuit performance and the VCO speed. If i use passive filter, the area will be too large. The external power supply is 1V+-10% and target vreg is 0.95V-0.9V. Any suitable regulator topology?

Thanks in advance
sj

 

[keith1200rs]

I don't see why you shouldn't design one with 50mV dropout. I did one several years ago with 35mV dropout. Looking at my notes it was only limited by the size of the PMOS I used - larger PMOS = smaller dropout.

Keith.

 

[sjamil02]

Cheers Keith.

 

[keith1200rs]

Two things to watch out for are stability and to make sure you have enough working range in the feedback amplifier. My initial circuit ideas dropped out too early I think and my final circuit used a folded cascode feedback amplifier.

Keith.

 

[erikl]

... only limited by the size of the PMOS

With an W/L=11000 LDPMOS (it had to stand 28V) we got a w.c. dropout voltage of 140mV @ 10mA & 4.5V .

 

[keith1200rs]

Wow, that's large. My design was on 0.8um and was designed for 1mA continuous which it managed at <50mV with 400/0.8um. It was a low voltage battery application.

Keith.

 

[erikl]

That was the price for the 35V LDPMOS. And still with Lmin=2.6µm in a 180nm process!