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Recent content by shwetha100

  1. S

    systemverilog interview questions post ur answers for these

    Can I not declare variables as rand or randc if the variables are inside a function within a class?/ ex: class example --- ---- function void test(); rand integer x; endfunction endclass The above code gives me error saying rand cannot be used in this context. Is it because I cannot declare...
  2. S

    An overview of SystemVerilog 3.1

    Can I not declare variables as rand or randc if the variables are inside a function within a class?/ ex: class example --- ---- function void test(); rand integer x; endfunction endclass The above code gives me error saying rand cannot be used in this context. Is it because I cannot declare...
  3. S

    Any good books for VLSI Interviews?

    Hi Attached are 2 text books that I used during a course.. a few chapters from these text books talk about MISR. hope that helps.
  4. S

    Any good books for VLSI Interviews?

    The first one was front end verification using system verilog but now I am in DFT.. Thanks for the book! Cheers!
  5. S

    Any good books for VLSI Interviews?

    I am into Digital Design. Please let me know if you know of any helpful books/links.
  6. S

    Any good books for VLSI Interviews?

    Thank you very much!! I looked at both the books and their indices indicate that they have a lot of useful stuff, I will read them. :) Thanks again
  7. S

    Any good books for VLSI Interviews?

    Hi I have attended a lot of interviews and have made it to two internships and I am now trying for a full time position. Since Novermber & December do not see a lot of hiring, I want to use this time to follow a strategic preparation for interviews. Do any of you know of any good books on VLSI...
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    difference between c and verilog

    Hi Vijay, Verilog is concurrent whereas C is sequential.
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    What exactly is the At Speed Test ?

    Can someone clearly explain what at speed test is? I have found similar posts on this website but couldn't get to a post where I understood what it is all about. Thanks.
  10. S

    Why OOP concepts are asked in verification positions?

    Thank you very much. That was helpful. I fyou know of any frequewsntly asked interview questions in this field, please post them here. Thank You.
  11. S

    Why do we write a golden model in C/C++ ?

    Re: Golden model? Thank You so much!!
  12. S

    Why OOP concepts are asked in verification positions?

    I have recently faced a few verifcation interviews and I was asked about a lot of software questions in OOP concepts, why would verification positions require that? I understand that, system verilog, used for verification is OOP oriented but why should we know about how compiler handles...
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    Why do we write a golden model in C/C++ ?

    Hello, I want to know more about this golden model stuff.. I know that when hardware spec is available, first thing to be done is to write a golden model for it in C/C++. What I am not sure about is why we have to this?? Why can we not write the verilog code for design directly????
  14. S

    system verilog for design 2nd edition by stuart sutherland

    HI, Can anyone upload the system verilog for deisgn, second edition book by stuart sutherland. That will be of great help. Thanks.
  15. S

    What does IP mean apart from Internet protocol?

    In Hardware industry when we talk about the verification of a particular block of IP, what does IP mean in this sense? I know IP means Internet Protocol but that does not seem appropriate here.
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